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enhanced a/d flash mcu with lcd & eeprom HT67F4892 revision: v1.00 date: ? ove ?? e ? ??? ? 01 ? ? ove ?? e ? ??? ? 01 ?
rev. 1.00 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? iphe ? al featu ? es ................................................................................................................. 7 gene?al desc?iption ......................................................................................... 8 block diag?a? .................................................................................................. 8 pin assign?ent ........... ..................................................................................... 9 pin desc?iption .......... ..................................................................................... 11 a?solute maxi?u? ratings .......................................................................... 1? d.c. cha?acte?istics ....................................................................................... 15 a.c. cha?acte?istics ....................................................................................... 17 a/d conve?te? elect?ical cha?acte?istics ........... .......................................... 18 refe?ence voltage cha?acte?istics ........... .................................................... 18 lvd/lvr elect?ical cha?acte?istics .............................................................. 19 powe?-on reset cha?acte?istics ........... ........................................................ 19 syste? a?chitectu?e ...................................................................................... ?0 clocking and pipelining ......................................................................................................... ? 0 p ? og ? a ? counte ? ................................................................................................................... ? 1 stack ..................................................................................................................................... ? 1 a ? ith ? etic and logic unit C alu ........................................................................................... ?? flash p?og?a? me?o?y ................................................................................. ?3 st ? uctu ? e ................................................................................................................................ ? 3 special vecto ? s ..................................................................................................................... ? 3 look-up ta ? le ............. .......................................................................................................... ? 3 ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ?? in ci ? cuit p ? og ? a ?? ing C icp ............................................................................................... ? 5 on-chip de ? ug suppo ? t C ocds ......................................................................................... ?? ram data me?o?y ......................................................................................... ?7 st ? uctu ? e ................................................................................................................................ ? 7 data me ? o ? y add ? essing ...................................................................................................... ? 8 gene ? al pu ? pose data me ? o ? y ............................................................................................ ? 8 special pu ? pose data me ? o ? y ............................................................................................. ? 8 special function registe? desc?iption ........................................................ 30 indi ? ect add ? essing registe ? s C iar0 ? iar1 ? iar ? ............................................................... 30 me ? o ? y pointe ? s C mp0 ? mp1l ? mp1h ? mp ? l ? mp ? h ......................................................... 30 accu ? ulato ? C acc .............................................................................................................. 31 p ? og ? a ? counte ? low registe ? C pcl ................................................................................. 3 ? look-up ta ? le registe ? s C tblp ? tbhp ? tblh .................................................................... 3 ? status registe ? C status ................................................................................................... 3 ?
rev. 1.00 ? ?ove??e? ??? ?01? rev. 1.00 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom eeprom data memory ........... ....................................................................... 34 eeprom data me ? o ? y st ? uctu ? e ........................................................................................ 3 ? eeprom registe ? s ............ .................................................................................................. 3 ? reading data f ? o ? the eeprom ......................................................................................... 3 ? w ? iting data to the eeprom ................................................................................................ 3 ? w ? ite p ? otection ..................................................................................................................... 3 ? eeprom inte ?? upt ............. ................................................................................................... 3 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 37 oscillators .......... ............................................................................................ 38 oscillato ? ove ? view ............. ................................................................................................. 38 system clock confgurations ............................................................................................... 38 exte ? nal high speed c ? ystal oscillato ? C hxt ...................................................................... 39 inte ? nal rc oscillato ? C hirc ............. .................................................................................. 39 exte ? nal 3 ? .7 ? 8 khz c ? ystal oscillato ? C lxt ............. .......................................................... ? 0 inte ? nal 3 ? khz oscillato ? C lirc ........................................................................................... ? 1 operating modes and system clocks ......................................................... 42 syste ? clocks ...................................................................................................................... ?? syste ? ope ? ation modes ...................................................................................................... ? 3 cont ? ol registe ? s .................................................................................................................. ?? ope ? ating mode switching .................................................................................................... ?? stand ? y cu ?? ent conside ? ations ........................................................................................... 50 wake-up ................................................................................................................................ 50 watchdog timer ........... .................................................................................. 51 watchdog ti ? e ? clock sou ? ce .............................................................................................. 51 watchdog ti ? e ? cont ? ol registe ? ............. ............................................................................ 51 watchdog ti ? e ? ope ? ation ................................................................................................... 5 ? reset and initialisation .................................................................................. 53 reset functions ............. ....................................................................................................... 53 reset initial conditions ........................................................................................................ 55 input/output ports ........................................................................................ 59 pull-high resisto ? s ................................................................................................................ 59 po ? t a wake-up ............. ........................................................................................................ ? 0 i/o po ? t cont ? ol registe ? s ..................................................................................................... ? 0 pin-sha ? ed functions ............. ............................................................................................... ? 1 i/o pin st ? uctu ? es .................................................................................................................. ? 1 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ? 1 timer modules C tm .......... ............................................................................ 62 int ? oduction ........................................................................................................................... ?? tm ope ? ation ............. ........................................................................................................... ?? tm clock sou ? ce ............. ...................................................................................................... ? 3 tm inte ?? upts ......................................................................................................................... ? 3 tm exte ? nal pins ................................................................................................................... ? 3 tm input/output pin cont ? ol registe ? ................................................................................... ?? p ? og ? a ?? ing conside ? ations ............. ................................................................................... ??
rev. 1.00 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom compact type tm C ctm .............................................................................. 67 co ? pact type tm ope ? ation ............. ................................................................................... ? 7 co ? pact type tm registe ? desc ? iption ................................................................................ ? 7 co ? pact type tm ope ? ating modes .................................................................................... 71 periodic type tm C ptm ............................................................................... 77 pe ? iodic type tm ope ? ation ................................................................................................. 77 pe ? iodic type tm registe ? desc ? iption ................................................................................ 78 pe ? iodic type tm ope ? ating modes ..................................................................................... 8 ? analog to digital converter C adc ........... .................................................... 91 a/d conve ? te ? ove ? view ....................................................................................................... 91 a/d conve ? te ? registe ? desc ? iption ...................................................................................... 91 a/d conve ? te ? ope ? ation ...................................................................................................... 95 a/d conve ? te ? refe ? ence voltage ......................................................................................... 9 ? a/d conve ? te ? input signals .................................................................................................. 9 ? conve ? sion rate and ti ? ing diag ? a ? .................................................................................. 97 su ?? a ? y of a/d conve ? sion steps ............. .......................................................................... 98 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 99 a/d conve ? sion function ............. ......................................................................................... 99 a/d conve ? sion p ? og ? a ?? ing exa ? ples ............. ............................................................... 100 serial interface module C sim ..................................................................... 102 spi inte ? face ...................................................................................................................... 10 ? i ? c inte ? face ............ ............................................................................................................. 111 lcd display memory ................................................................................... 121 lcd d ? ive ? output ............................................................................................................... 1 ? 1 lcd cont ? ol registe ? .......................................................................................................... 1 ?? lcd wavefo ?? .................................................................................................................... 1 ?? led driver .................................................................................................... 130 led d ? ive ? ope ? ation .......................................................................................................... 130 led d ? ive ? registe ? ............................................................................................................ 130 uart interface ............................................................................................. 131 uart exte ? nal pin inte ? facing ............................................................................................ 131 uart data t ? ansfe ? sche ? e .............................................................................................. 131 uart status and cont ? ol registe ? s .................................................................................... 13 ? baud rate gene ? ato ? .......................................................................................................... 138 uart setup and cont ? ol ..................................................................................................... 139 uart t ? ans ? itte ? ................................................................................................................ 1 ? 0 uart receive ? ............. ...................................................................................................... 1 ?? managing receive ? e ?? o ? s .................................................................................................. 1 ? 3 uart module inte ?? upt st ? uctu ? e ........................................................................................ 1 ?? uart powe ? down and wake-up ....................................................................................... 1 ?? interrupts ...................................................................................................... 147 inte ?? upt registe ? s ............................................................................................................... 1 ? 7 inte ?? upt ope ? ation .............................................................................................................. 153 exte ? nal inte ?? upt ............. .................................................................................................... 15 ?
rev. 1.00 ? ?ove??e? ??? ?01? rev. 1.00 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom a/d conve ? te ? inte ?? upt ....................................................................................................... 155 multi-function inte ?? upts ............. .......................................................................................... 155 se ? ial inte ? face module inte ?? upt ......................................................................................... 155 uart inte ?? upt ............. ....................................................................................................... 155 ti ? e base inte ?? upts ........................................................................................................... 15 ? eeprom inte ?? upt ............. ................................................................................................. 157 lvd inte ?? upt ....................................................................................................................... 157 ti ? e ? module inte ?? upts ............. ......................................................................................... 157 inte ?? upt wake-up function ................................................................................................. 158 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 158 low voltage detector C lvd .......... ............................................................. 159 lvd registe ? ............. .......................................................................................................... 159 lvd ope ? ation ..................................................................................................................... 1 ? 0 confguration options ................................................................................. 161 application circuits ........... .......................................................................... 162 instruction set .............................................................................................. 163 int ? oduction ......................................................................................................................... 1 ? 3 inst ? uction ti ? ing ................................................................................................................ 1 ? 3 moving and t ? ansfe ?? ing data ............................................................................................. 1 ? 3 a ? ith ? etic ope ? ations .......................................................................................................... 1 ? 3 logical and rotate ope ? ation ............................................................................................. 1 ?? b ? anches and cont ? ol t ? ansfe ? ........................................................................................... 1 ?? bit ope ? ations ..................................................................................................................... 1 ?? ta ? le read ope ? ations ....................................................................................................... 1 ?? othe ? ope ? ations ............. .................................................................................................... 1 ?? instruction set summary .......... .................................................................. 165 ta ? le conventions ............................................................................................................... 1 ? 5 extended inst ? uction set ............. ........................................................................................ 1 ? 7 instruction defnition ................................................................................... 169 ([whqghg,qvwuxfwlrqhqlwlrq ........................................................................................... 178 package information ................................................................................... 185 ? 8-pin lqfp (7 ?? 7 ?? ) outline di ? ensions .................................................................. 18 ? 5 ? -pin lqfp (1 ??? 1 ??? ) outline di ? ensions .............................................................. 187
rev. 1.00 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom features cpu features ? operating v oltage f sys =4mhz: 2.2v~5.5v f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =16mhz: 4.5v~5.5v ? up to 0.25 s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? four oscillators: high speed internal rc C hirc internal 32khz rc C lirc high speed external crystal C hxt external 32.768khz crystal C lxt ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 8mhz oscillator requires no external components ? all instructions executed in 1~3 instruction cycles ? table read instructions ? 115 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction
rev. 1.00 ? ?ove??e? ??? ?01? rev. 1.00 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom peripheral features ? flash program memory: 8k 16 ? ram data memory: 384 8 ? true eeprom memory: 64 8 ? watchdog t imer function ? up to 50 bidirectional i/o lines ? 4 pin-shared external interrupts ? multiple t imer modules for time measure, input capture, compare match output, pwm output or single pulse output function ? dual t ime-base functions for generation of fxed time interrupt signals ? 10-channel 12-bit resolution a/d converter ? lcd display: 32seg 4com & 32seg 8com for 52-pin lqfp package type 28seg 4com & 28seg 8com for 48-pin lqfp package type 1/3 or 1/4 bias ? led display: 8seg 8com ? serial interface module with spi and i 2 c interfaces ? full-duplex universal asynchronous receiver and t ranmitter interface C uart ? low v oltage reset function C lvr ? low v oltage detect function C lvd ? package type: 48/52-pin lqfp ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retenction > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years
rev. 1.00 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom general description the HT67F4892 is a flash memory a/d type 8-bit high performance risc architecture microcontroller, designed especially for applications that interface directly to analog signals, such as those from sensors. of fering users the convenience of flash memory multi-programming features, this devic e also includes a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter. multiple and extremely fexible t imer modules provi de t iming, pul se ge neration a nd pw m ge neration func tions. e asy c ommunication with the outside world is provided by including fully integrated spi, i 2 c functions, popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protec tive fe atures such as an internal w atchdog t imer, low v oltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a f ull c hoice o f e xternal, i nternal a nd h igh a nd l ow o scillators f unctions a re p rovided i ncluding t wo fully integrated system oscillators which require no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the uar t module is contained in the device. it can support the applications such as data communication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and battery operated device communication, etc. the inclusion of both lcd and led driver functions allows for easy and cost ef fective solutions in appl ications t hat require i nterface t o t hese displ ay t ypes. in addi tion, t he i nclusion of fle xible i/o programming features, t ime-base functions along with many other features ensure that only a minimum of external components is required for application implementation, resulting in reduced component costs and reductions in circuit board areas. block diagram 8-?it risc mcu co?e i/o ti?e? modules flash p?og?a? me?o?y eeprom data me?o?y flash/eeprom p?og?a??ing ci?cuit?y ram data me?o?y ti?e bases low voltage reset watchdog ti?e? inte??upt cont?olle? reset ci?cuit exte?nal hxt/lxt oscillato?s sim (i ? c/spi) 1?-?it a/d conve?te? uart low voltage detect inte?nal hirc/lirc oscillato?s led d?ive? lcd d?ive?
rev. 1.00 8 ?ove??e? ??? ?01? rev. 1.00 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin assignment vss/avss pf?/seg1?/rx pf?/seg18/i?t0 pf5/seg17/tx pf7/seg19/i?t1/tp0_1 vdd/avdd pa5/xt? pg0/seg?? HT67F4892/ht67v4892 48 lqfp-a 1 ? 3 ? 5 ? 7 8 9 10 11 1? 13 1? 15 1? 17 18 19 ?0 ?1 ?? ?3 ?? ?5 ?? ?7 ?8 ?9 30 31 3? 33 3? 35 3? ?5 ?? ?7?8 37 3839 ?0?1 ?? ?3?? pa?/xt1 pa?/seg?? pa0/seg?0/i?t?/tck0/ocdsda/icpda pa?/seg?1/i?t3/tp0_0/ocdsck/icpck pg?/seg?5 pa7/seg?7 pb5/a?9 pe7/a?8/com7 pb?/a?7/vref pe?/a??/com? pe5/a?5/com5/tck? pe?/a??/com?/tck1 pb3/a?3/tp1 pb?/a??/tp? pb1/a?1/tp3 pb0/a?0/tck3 pe3/com3 pe?/com? pe1/com1 pe0/com0 pd0/seg0 pd1/seg1 pd?/seg? pd3/seg3 pd?/seg? pd5/seg5 pd?/seg? pg?/seg?8 pa1/osc? pa3/osc1 pc7/seg15/sck/scl pc?/seg1?/scs pc5/seg13/sdo pc?/seg1?/sdi/sda pc3/seg11 pc?/seg10 pc1/seg9 pc0/seg8 pd7/seg7 pg?/seg30
rev. 1.00 10 ? ove ?? e ? ??? ? 01 ? rev. 1.00 11 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom vss/avss pf?/seg1?/rx pf?/seg18/i?t0 pf5/seg17/tx pf7/seg19/i?t1/tp0_1 vdd/avdd pa5/xt? pg0/seg?? pa?/xt1 pa?/seg?? pa0/seg?0/i?t?/tck0/ocdsda/icpda pa?/seg?1/i?t3/tp0_0/ocdsck/icpck pg?/seg?5 pa7/seg?7 pb5/a?9 pe7/a?8/com7 pb?/a?7/vref pe?/a??/com? pe5/a?5/com5/tck? pe?/a??/com?/tck1 pb3/a?3/tp1 pb?/a??/tp? pb1/a?1/tp3 pb0/a?0/tck3 pe3/com3 pe?/com? pe1/com1 pe0/com0 pd0/seg0 pd1/seg1 pd?/seg? pd3/seg3 pd?/seg? pd5/seg5 pd?/seg? pg?/seg?8 1 ? 3 ? 5 ? 7 8 9 10 11 1? 13 1? 15 1? 17 18 19 ?0 ?1 ?? ?3 ?? ?5 ?? ?7 ?8 ?9 30 31 3? 33 3? 35 3? ?5 ???7 ?8 37 38 39 ?0 ?1?? ?3?? ?9 5051 5? HT67F4892/ht67v4892 52 lqfp-a pg1/seg?3 pg3/seg?? pg5/seg?9 pa1/osc? pa3/osc1 pc7/seg15/sck/scl pc?/seg1?/scs pc5/seg13/sdo pc?/seg1?/sdi/sda pc3/seg11 pc?/seg10 pc1/seg9 pc0/seg8 pd7/seg7 pg7/seg31 pg?/seg30 note: 1. if the pin-shared pin functi ons have multiple outputs simultaneously , its pin names at the right side of the "/" sign can be used for higher priority. 2. the ocdsda and ocdsck pins are supplied as dedicated ocds pins and as such only available for the ht67v4892 device which is the ocds ev chip for the HT67F4892 device.
rev. 1.00 10 ?ove??e? ??? ?01? rev. 1.00 11 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin description with the exception of the pow er pins and s ome relavant transformer control pins, all pins on the device can be referenced by its port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of t he pi ns. howe ver t hese port pi ns a re a lso sha red wi th ot her func tion suc h a s t he ana log t o digital converter , t imer module pins etc. the function of each pin is listed in the following table, howeve r t he de tails be hind how e ach pi n i s c onfgured i s c ontained i n ot her se ctions of t he datasheet. note that where more than one package type exists the table will refect the situation for the larger package type. pin name function opt i/t o/t description pa0/seg ? 0/i ? t ? / tck0/ocdsda/ icpda pa0 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. seg ? 0 segcr ? a ? lcd seg ? ent output i ? t ? i ? teg i ? tc ? st exte ? nal inte ?? upt ? tck0 st tm0 clock input ocdsda st cmos ocds add ? ess/data ? fo ? ev chip only icpda st cmos icp add ? ess/data pa1/osc ? pa1 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. osc ? co hxt hxt output pin pa ? /seg ? 1/i ? t3/ tp0_0/ocdsck/ icpck pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. seg ? 1 segcr ? a ? lcd seg ? ent output i ? t3 i ? teg i ? tc ? st exte ? nal inte ?? upt 3 tp0_0 tmpc st cmos tm0 i/o ocdsck st ocds clock ? fo ? ev chip only icpck st icp clock pa3/osc1 pa3 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. osc1 co hxt hxt input pin pa ? /xt1 pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. xt1 fsubc lxt lxt input pin pa5/xt ? pa5 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. xt ? fsubc lxt lxt output pin pa ? /seg ?? pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. seg ?? segcr3 a ? lcd seg ? ent output pa7/seg ? 7 pa7 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. seg ? 7 segcr3 a ? lcd seg ? ent output pb0/a ? 0/tck3 pb0 pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 0 acerl a ? adc input channel 0 tck3 st tm3 clock input pb1/a ? 1/tp3 pb1 pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 1 acerl a ? adc input channel 1 tp3 tmpc st cmos tm3 i/o
rev. 1.00 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 13 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin name function opt i/t o/t description pb ? /a ?? /tp ? pb ? pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ?? acerl a ? adc input channel ? tp ? tmpc st cmos tm ? i/o pb3/a ? 3/tp1 pb3 pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 3 acerl a ? adc input channel 3 tp1 tmpc st cmos tm1 i/o pb ? /a ? 7/vref pb ? pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 7 acerl a ? adc input channel 7 vref adcr1 a ? adc ? efe ? ence voltage input pin pb5/a ? 9 pb5 pbpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 9 acerh a ? adc input channel 9 pc0/seg8 pc0 pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg8 segcr1 a ? lcd seg ? ent output pc1/seg9 pc1 pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg9 segcr1 a ? lcd seg ? ent output pc ? /seg10 pc ? pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg10 segcr1 a ? lcd seg ? ent output pc3/seg11 pc3 pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg11 segcr1 a ? lcd seg ? ent output pc ? /seg1 ? /sdi/sda pc ? pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg1 ? segcr1 a ? lcd seg ? ent output sdi simc0 st spi se ? ial data input sda simc0 st ? mos i ? c data line pc5/seg13/sdo pc5 pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg13 segcr1 a ? lcd seg ? ent output sdo simc0 cmos spi se ? ial data output pc ? /seg1 ? / scs pc ? pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg1 ? segcr1 a ? lcd seg ? ent output scs simc0 simc ? st cmos spi slave select pin pc7/seg15/sck/ scl pc7 pcpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg15 segcr1 a ? lcd seg ? ent output sck simc0 st cmos spi se ? ial clock scl simc0 st ? mos i ? c clock line pd0/seg0 pd0 pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg0 segcr0 a ? lcd seg ? ent output pd1/seg1 pd1 pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg1 segcr0 a ? lcd seg ? ent output pd ? /seg ? pd ? pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? segcr0 a ? lcd seg ? ent output pd3/seg3 pd3 pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg3 segcr0 a ? lcd seg ? ent output pd ? /seg ? pd ? pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? segcr0 a ? lcd seg ? ent output pd5/seg5 pd5 pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg5 segcr0 a ? lcd seg ? ent output pd ? /seg ? pd ? pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? segcr0 a ? lcd seg ? ent output
rev. 1.00 1? ?ove??e? ??? ?01? rev. 1.00 13 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin name function opt i/t o/t description pd7/seg7 pd7 pdpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg7 segcr0 a ? lcd seg ? ent output pe0/com0 pe0 pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. com0 lcdc0 a ? lcd co ?? o ? output pe1/com1 pe1 pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. com1 lcdc0 a ? lcd co ?? o ? output pe ? /com ? pe ? pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. com ? lcdc0 a ? lcd co ?? o ? output pe3/com3 pe3 pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. com3 lcdc0 a ? lcd co ?? o ? output pe ? /a ?? /com ? / tck1 pe ? pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ?? acerl a ? adc input channel ? com ? lcdc0 a ? lcd co ?? o ? output tck1 st tm1 clock input pe5/a ? 5/com5/ tck ? pe5 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 5 acerl a ? adc input channel 5 com5 lcdc0 a ? lcd co ?? o ? output tck ? st tm ? clock input pe ? /a ?? /com ? pe ? pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ?? acerl a ? adc input channel ? com ? lcdc0 a ? lcd co ?? o ? output pe7/a ? 8/com7 pe7 pepu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. a ? 8 acerl a ? adc input channel 8 com7 lcdc0 a ? lcd co ?? o ? output pf ? /seg1 ? /rx pf ? pfpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg1 ? segcr ? a ? lcd seg ? ent output rx ucr1 st uart rx se ? ial data input pin pf5/seg17/tx pf5 pfpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg17 segcr ? a ? lcd seg ? ent output tx ucr1 cmos uart tx se ? ial data output pin pf ? /seg18/i ? t0 pf ? pfpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg18 segcr ? a ? lcd seg ? ent output i ? t0 i ? teg i ? tc0 st exte ? nal inte ?? upt 0 pf7/seg19/i ? t1/ tp0_1 pf7 pfpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg19 segcr ? a ? lcd seg ? ent output i ? t1 i ? teg i ? tc0 st exte ? nal inte ?? upt 1 tp0_1 tmpc st cmos tm0 i/o pg0/seg ?? pg0 pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ?? segcr ? a ? lcd seg ? ent output pg1/seg ? 3 pg1 pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? 3 segcr ? a ? lcd seg ? ent output pg ? /seg ? 5 pg ? pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? 5 segcr3 a ? lcd seg ? ent output pg3/seg ?? pg3 pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ?? segcr3 a ? lcd seg ? ent output
rev. 1.00 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 15 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin name function opt i/t o/t description pg ? /seg ? 8 pg ? pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? 8 segcr3 a ? lcd seg ? ent output pg5/seg ? 9 pg5 pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg ? 9 segcr3 a ? lcd seg ? ent output pg ? /seg30 pg ? pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg30 segcr3 a ? lcd seg ? ent output pg7/seg31 pg7 pgpu st cmos gene ? al pu ? pose i/o.registe ? ena ? led pull-high. seg31 segcr3 a ? lcd seg ? ent output vdd/avdd vdd pwr digital positive powe ? supply avdd pwr analog positive powe ? supply vss/avss vss pwr digital negative powe ? supply avss pwr analog negative powe ? supply legend: i/t: input type; o/t: output type; opt: optional by confguration options (co) or register option; pwr: power; st: schmitt t rigger input; an: analog signal cmos: cmos output; nmos: nmos output; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: these are stress ratings only . stresses exceeding the range specified under "absolute maximum rating s" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.00 1? ?ove??e? ??? ?01? rev. 1.00 15 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom d.c. characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hxt) f sys =f hxt = ? mhz ? . ? 5.5 v f sys =f hxt =8mhz ? . ? 5.5 f sys =f hxt =1 ? mhz ? .7 5.5 f sys =f hxt =1 ? mhz ? .5 5.5 ope ? ating voltage (hirc) f sys =f hirc =8mhz ? . ? 5.5 ope ? ating voltage (lxt) f sys =f lxt =3 ? .7 ? 8khz ? . ? 5.5 ope ? ating voltage (lirc) f sys =f lirc =3 ? khz ? . ? 5.5 i dd ope ? ating cu ?? ent ? ? ormal mode 3v ? o load ? f h =8mhz ? adc off ? wdt ena ? le f sys =f h ? f sub =f lxt o ? f lirc 1. ? ? . ? ? a 5v 3.3 5.0 ope ? ating cu ?? ent (hxt) 3v ? o load ? f sys =f h / ?? adc off ? wdt ena ? le 0.9 1.5 ? a 5v ? .5 3.75 3v ? o load ? f sys =f h / ?? adc off ? wdt ena ? le 0.7 1.0 5v ? .0 3.0 3v ? o load ? f sys =f h /8 ? adc off ? wdt ena ? le 0. ? 0.9 5v 1. ? ? . ? 3v ? o load ? f sys =f h /1 ?? adc off ? wdt ena ? le 0.5 0.75 5v 1.5 ? . ? 5 3v ? o load ? f sys =f h /3 ?? adc off ? wdt ena ? le 0. ? 9 0.7 ? 5v 1. ? 5 ? .18 3v ? o load ? f sys =f h / ??? adc off ? wdt ena ? le 0. ? 7 0.71 5v 1. ? ? .1 ope ? ating cu ?? ent ? slow mode (lxt ? lirc) 3v ? o load ? f sys =f sub =f lxt =3 ? 7 ? 8hz ? adc off ? wdt ena ? le ? lxtlp=0 ? lvr ena ? le ? 5 75 a 5v 90 1 ? 0 3v ? o load ? f sys =f sub =f lxt =3 ? 7 ? 8hz ? adc off ? wdt ena ? le ? lxtlp=1 ? lvr ena ? le ? 0 70 a 5v 85 135 3v ? o load ? f sys =f sub =f lirc =3 ? khz ? adc off ? wdt ena ? le ? lvr ena ? le ? 0 ? 5 a 5v 80 130
rev. 1.00 1 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 17 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i stb idle0 mode stand ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=0 ? ? a 5v ? 8 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 1.5 3.0 5v 3.0 ? .0 idle0 mode stand ? y cu ?? ent (lirc on) 3v ? o load ? adc off ? wdt ena ? le 1.5 3.0 a 5v 3.0 ? .0 idle0 mode stand ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le ? (r t =1170k without quick cha ? ge ? v lcd =v dd ) 3.0 ? .0 a 5v ? .0 1 ? 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le ? (r t =225k without quick charge, v lcd =v dd ) 1 ? ? 8 5v ?? ? 8 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le ? (r t =1170k with quick charge, qct[ ? :0]=0 ? v lcd =v dd ) 5 10 5v 9 18 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le ? (r t =1170k with quick charge, qct[ ? :0]=7 ? v lcd =v dd ) 11 ?? 5v 18 3 ? idle1 mode stand ? y cu ?? ent (lirc on) 3v ? o load ? adc off ? wdt ena ? le ? f sys =8mhz on 0.5 3.0 ? a 5v 1.0 ? .0 sleep0 mode stand ? y cu ?? ent (lxt o ? lirc off) 3v ? o load ? adc off ? wdt disa ? le 0. ? 1.0 a 5v 0. ? ? .0 sleep1 mode stand ? y cu ?? ent (lxt o ? lirc on) 3v ? o load ? adc off ? wdt ena ? le 1.5 3.0 a 5v ? .5 5.0 v il1 input low voltage fo ? i/o po ? ts 0 0.3 v dd v v ih1 input high voltage fo ? i/o po ? ts 0.7 v dd v dd v gpio (except for pd0~pd7 & pe0~pe7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd ? 8 ? a 5v v ol =0.1v dd 10 ? 0 i oh i/o po ? t sou ? ce cu ?? ent 3v v oh =0.9v dd - ? - ? ? a 5v v oh =0.9v dd -5 -10 high sink i/o for led driver (pe0~pe7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 8 1 ? ? a 5v v ol =0.1v dd ? 0 ? 0 i oh i/o po ? t sou ? ce cu ?? ent 3v v oh =0.9v dd - ? - ? ? a 5v v oh =0.9v dd -5 -10 adjustable source i/o for led driver (pd0~pd7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd ? 8 ? a 5v v ol =0.1v dd 10 ? 0
rev. 1.00 1? ?ove??e? ??? ?01? rev. 1.00 17 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i oh i/o po ? t sou ? ce cu ?? ent 3v v oh =0.9v dd (iohsn[1:0]=00b ? n=0~7) - ? - ? ? a v oh =0.9v dd (iohsn[1:0]=01b ? n=0~7) -0. ? 7 -1.33 v oh =0.9v dd (iohsn[1:0]=10b ? n=0~7) -0.5 -1 v oh =0.9v dd (iohsn[1:0]=11b ? n=0~7) -0.33 -0. ?? 5v v oh =0.9v dd (iohsn[1:0]=00b ? n=0~7) -5 -10 v oh =0.9v dd (iohsn[1:0]=01b ? n=0~7) -1. ? 7 -3.33 v oh =0.9v dd (iohsn[1:0]=10b ? n=0~7) -1. ? 5 - ? .5 v oh =0.9v dd (iohsn[1:0]=11b ? n=0~7) -0.83 -1. ? 7 r ph pull-high resistance fo ? i/o po ? ts 3v ? 0 ? 0 100 k 5v 10 30 50 r t lcd total bias resisto ? 3v/5v -30 r t +30 % i tol total i/o po ? t sink cu ?? ent 5v 80 ? a i toh total i/o po ? t sou ? ce cu ?? ent 5v -80 ? a a.c. characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? . ? ~5.5v dc ? mhz ? . ? ~5.5v dc 8 ? .7~5.5v dc 1 ? ? .5~5.5v dc 1 ? f sys syste ? clock (hirc) ? . ? v~5.5v 8 mhz f hirc 8mhz w ? ite ? t ? i ?? ed hirc frequency 3v/5v ta= ? 5 c -1% 8 +1% mhz ta=- ? 0~85 c - ? % 8 + ? % ? . ? v~5.5v ta= ? 5 c - ? .5% 8 + ? .5% ta=- ? 0 c ~ 85c -3% 8 +3% f lirc syste ? clock (lirc) 5v ta= ? 5 c -10% 3 ? +10% khz t timer tckn input pulse width 0.3 s t i ? t inte ?? upt pulse width 10 s t eerd eeprom ? ead ti ? e 5v ? ? t sys t eewr eeprom w ? ite ti ? e 5v ? ? ? s t rstd syste ? reset delay ti ? e (por reset ? lvr ha ? dwa ? e reset ? lvr softwa ? e reset ? wdt softwa ? e reset) ? 5 50 100 ? s syste ? reset delay ti ? e (wdt ti ? e-out ha ? dwa ? e cold reset) 8.3 1 ? .7 33.3 ? s
rev. 1.00 18 ? ove ?? e ? ??? ? 01 ? rev. 1.00 19 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions t sst syste ? sta ? t-up ti ? e ? pe ? iod (powe ? on reset) f sys =f hirc 10 ?? t hirc f sys =f hxt 10 ?? t hxt syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? powe ? down mode whe ? e f sys is off) f sys =f lxt 10 ?? t lxt f sys =f hxt ~ f hxt / ?? 10 ?? t hxt f sys =f hirc ~ f hirc / ?? 1 ? t hirc f sys =f lirc ? t lirc syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? powe ? down mode whe ? e f sys is on) f sys =f h ~ f h / ??? f h =f hxt o ? f hirc ? f h f sys =f lxt o ? f lirc ? f sub t sreset softwa ? e reset width to reset ? 5 90 1 ? 0 s 1rwh w sys sys dd h dffudf h hudo foodu uhhf d hfso fdsdfu o h fhfh hhh d 66 d ofdh d foh h hyfh d soh a/d converter electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d conve ? te ? ope ? ating voltage ? .7 5.5 v v adi a/d conve ? te ? input voltage 0 av dd / v ref v v ref a/d conve ? te ? refe ? ence voltage ? av dd v d ? l diffe ? ential ? on-linea ? ity 3v v ref =v dd ? t adck =0.5s - ? + ? lsb 5v v ref =v dd ? t adck =0.5s 3v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i ? l integ ? al ? on-linea ? ity 3v v ref =v dd ? t adck =0.5s -7 +7 lsb 5v v ref =v dd ? t adck =0.5s 3v v ref =v dd ? t adck =10s 5v v ref =v dd ? t adck =10s i adc additional cu ?? ent fo ? adc ena ? le 3v ? o load (t adck =0.5s) 0.9 1.35 ? a 5v ? o load (t adck =0.5s) 1. ? 1.8 t adck a/d conve ? te ? clock pe ? iod 0.5 10 s t o ?? st adc on-to-sta ? t ti ? e ? s t ads a/d conve ? te ? sa ? pling ti ? e ? t adck t adc conve ? sion ti ? e (include adc sa ? ple and hold ti ? e) 1 ? - ? it adc 1 ? t adck reference voltage characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v bg refe ? ence with buffe ? voltage -3% 1.09 +3% v i bg addition powe ? consu ? ption if v bg refe ? ence with buffe ? is used ? 00 300 a t bgs v bg tu ? n on sta ? le ti ? e ? 00 s 1rwh 7kh 9 %* yrowdjh lv xvhg dv wkh ' frqyhuwhu lqwhuqdo vljqdo lqsxw
rev. 1.00 18 ?ove??e? ??? ?01? rev. 1.00 19 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lvd/lvr electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ? le ? voltage select ? .1v - 5% ? .1 + 5% v lvr ena ? le ? voltage select ? .55v - 5% ? .55 + 5% lvr ena ? le ? voltage select 3.15v - 5% 3.15 + 5% lvr ena ? le ? voltage select 3.8v - 5% 3.8 + 5% v lvd low voltage detection voltage lvd ena ? le ? voltage select ? .0v - 5% ? .0 + 5% v lvd ena ? le ? voltage select ? . ? v - 5% ? . ? + 5% lvd ena ? le ? voltage select ? . ? v - 5% ? . ? + 5% lvd ena ? le ? voltage select ? .7v - 5% ? .7 + 5% lvd ena ? le ? voltage select 3.0v - 5% 3.0 + 5% lvd ena ? le ? voltage select 3.3v - 5% 3.3 + 5% lvd ena ? le ? voltage select 3. ? v - 5% 3. ? + 5% lvd ena ? le ? voltage select ? .0v - 5% ? .0 + 5% i lvd additional powe ? consu ? ption if lvd is used 3v lvd disable lvd enable (lvr ena ? le) 30 ? 5 a 5v ? 0 90 t lvds lvdo sta ? le ti ? e for lvr enable, lvd off on 15 s t lvr mini ? u ? low voltage width to reset 1 ? 0 ?? 0 ? 80 s t lvd mini ? u ? low voltage width to inte ?? upt ? 0 1 ? 0 ?? 0 s power-on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr por v dd rising rate to ensu ? e powe ? -on reset 0.035 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s v dd t por rr por v por ti?e
rev. 1.00 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom system architecture a key factor in the high-performan ce features of the range of microcontrollers is attributed to their internal system architecture. the device takes advantage of the usual features found within risc microcontrollers providing increase d speed of operation and enhanced performance. the pipelining scheme i s i mplemented i n su ch a wa y t hat i nstruction f etching a nd i nstruction e xecution a re overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or extended instructions respectively . the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , lxt , hirc or lirc oscillator is subdivided into four internall y generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fetch inst. (pc) (syste? clock) f sys phase clock t1 phase clock t? phase clock t3 phase clock t? p?og?a? counte? pc pc+1 pc+? pipelining execute inst. (pc-1) fetch inst. (pc+1) execute inst. (pc) fetch inst. (pc+?) execute inst. (pc+1) system clocking and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
rev. 1.00 ?0 ?ove??e? ??? ?01? rev. 1.00 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom fetch inst. 1 1 mov a?[1?h] ? call delay 3 cpl [1?h] ? : 5 : ? delay: ?op execute inst. 1 fetch inst. ? execute inst. ? fetch inst. 3 flush pipeline fetch inst. ? execute inst. ? fetch inst. 7 instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demands a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc1 ? ~pc8 pcl7~pcl0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly . however , as only this low byte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only . the stack is or ganized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack.
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom stack pointe? stack level ? stack level 1 stack level 3 : : : stack level 8 p?og?a? me?o?y p?og?a? counte? botto? of stack top of stack if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc lrr, lrra, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement: inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti lsnz, lsz, lsza, lsiz, lsiza, lsdz, lsdza
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, the flash device of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. structure the progra m me mory ha s a c apacity of 8k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. initialisation secto? 0000h 000?h 0030h 1fffh inte??upt vecto?s 1? ?its program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 0000h i s re served for use by t he de vice re set for progra m i nitialisation. aft er a de vice re set i s initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the corresponding table read instruction such as "tabrd [m]" or "tabrdl [m]" respectively when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as "ltabrd [m]" or "l tabrdl [m]" respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom last page o? tbhp registe? add?ess tblp registe? data 1? ?its p?og?a? me?o?y registe? tblh use? selected registe? high byte low byte table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller . this example us es raw table data located in the p rogram m emory w hich is stored there using the org statement. the value at this org statement is "1f00h" which refers to the start address of the last page within the 8k program memory of the microcontroller . the table pointer low byte register is setup here to ha ve an initial val ue of "06h". this will ensure that the frst d ata r ead f rom t he d ata t able wi ll b e a t t he pr ogram me mory a ddress "1 f06h" o r 6 l ocations after the start of the last page. note that the value for the table pointer is referenced to the address specifed by tblp and tbhp if the "t abrd [m]" or "l tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" or "ltabrd [m]" instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,1fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "1f06h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "1f05h" transferred to ; tempreg2 and tblh in this example the data "1ah" is ; transferred to tempreg1 and data "0fh" to register tempreg2 : : org 1f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, a means of programming the microcontroller in-circuit has provided using a 4-pin interface. this provides manufacturers with the possibil ity of manufacturing their circ uit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the flash mcu to w riter programming pin correspondence table is as follows: writer pins mcu programming pins pin description icpda pa0 p ? og ? a ?? ing se ? ial data/add ? ess icpck pa ? p ? og ? a ?? ing clock vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. * * w?ite?_vdd icpda icpck w?ite?_vss to othe? ci?cuit vdd pa0 pa? vss w?ite? connecto? signals mcu p?og?a??ing pins 1rwh pd eh uhvlvwru ru fdsdflwru 7kh uhvlvwdqfh ri pxvw eh juhdwh u wkdq ? ru wkh fdsdflwdqfh ri pxvw eh ohvv wkdq q)
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an "on- chip de bug" f unction t o d ebug t he d evice d uring t he d evelopment p rocess. t he e v c hip a nd t he actual mcu device are almost functionally compatible except for the "on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda a nd ocdsck pi ns t o t he ht -ide de velopment t ools. t he ocdsda pi n i s t he ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the act ual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". e-link pins ev chip pins pin description ocdsda ocdsda on-chip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on-chip de ? ug suppo ? t clock input vdd vdd powe ? supply vss vss g ? ound
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. categorized into three types, the frst of these is an area of ram where special function registers are located. t hese r egisters h ave fx ed l ocations a nd a re n ecessary f or c orrect o peration o f t he d evice. many of these registers can be read from and written to directly under program control, however , some remain protecte d from use r manipulation. the second area of data memory is reserved for general purpose use . al l l ocations wi thin t his a rea a re re ad a nd wri te a ccessible unde r progra m control. the third area is used for the lcd data memory . this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly af fect the displayed data. structure the da ta me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de ram. each of the d ata m emory s ector is categorized into tw o types , the s pecial p urpose d ata memory and t he ge neral purpose da ta me mory. whi le t he 80h~9fh of se ctor 1 i s lcd da ta memory. the start address of the data memory for the device is the address 00h. switching between the different data memory sectors is achieved by setting the memory pointers to the correct value. special purpose data memory lcd data memory general purpose data memory available sectors capacity sector: address capacity sector: address 0 ? 1 ??? 3 3 ? 8 1: 80h~9fh 38 ? 8 0: 80h~ffh ? : 80h~ffh 3: 80h~ffh data memory summary 00h 7fh 80h ffh special pu?pose data me?o?y gene?al pu?pose data me?o?y secto? 0 secto? 1 secto? 1 lcd data me?o?y secto? ? 9fh ?0h: eec (only availa?le in secto? 1) secto? 3 data me?o?y st?uctu?e
rev. 1.00 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom data memory addressing for the device that supports the extended instructions, there is no bank pointer for data memory addressing. for data memory the desired sector is pointed by the mp1h or mp2h register and the certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory s ectors except s ector 0, the extended ins tructions can be us ed to acces s the data memory instead o f u sing t he i ndirect a ddressing a ccess. t he m ain d ifference b etween st andard i nstructions and extended instructions is that the data memory address "m" in the extended instructions has 10 valid bits dependi ng on which device is selected, the high byte indica tes a sector and the low byte indicates a specifc address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and wr iting o perations. b y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value "00h".
rev. 1.00 ?8 ?ove??e? ??? ?01? rev. 1.00 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom 00h iar 0 01h mp 0 0?h iar 1 03h mp 1l 0?h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch 0 dh tm 1c1 0 eh 0 fh 10h tbc 11h tm 1 dl 1?h 19h ctrl 18h fsubc 1 bh 1 ah 1 dh 1 ch 1 fh lvdc 13h 1?h tm 1 ah 15h i?tc 3 1?h 17h tm 1 dh eea tm ? ah pawu ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ??h ?5h ??h ?7h tmpc tm ?c0 ?0h ?1h ??h ?3h ??h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 50h 51h 5?h 53h 5?h eed tm 0c1 1 eh tm 1 al tm ?c1 55h 5?h ?0h ?1h ??h ?3h ??h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 70h tm 0 dl tm 0 dh 30h 31h 3?h 38h 3 ch 33h 3?h 35h 3?h 37h tm 0 al tm 0 ah tm 0 rph 3 bh 39h 3 ah 71h 7?h 73h 7?h 75h 7?h mfi 1 mfi ? mfi 0 3 dh 3 fh 3 eh mp 1h iar ? mp ?l mp ?h smod wdtc i?teg i?tc 1 i?tc ? mfi 3 papu pa pac pbpu pb tm ? dl tm 3 dl tm 3c0 tm 3c1 tm 3 ah tm 3 al 57h lcdc 0 58h 59h lcdc 1 5 ah segcr 0 5 bh 5 ch 5 dh 5 eh 5 fh pcc pdpu pd pdc pe pe c pfpu pf pfc pgpu pg pgc simc 0 simc 1 simd sima / simc ? tm ? al 78h 7 ch 77h 7 bh 79h 7 ah 7 dh 7 fh 7 eh iohr 0 iohr 1 mfi ? adcr 0 acerh segcr 1 segcr ? segcr 3 pcpu pc pepu lvrc adrl adrh secto? 0???3 secto? 1 secto? 0???3 secto? 1 eec ucr 1 usr ucr ? brg txr / rxr i?tc 0 pbc acerl adcr 1 tm 0c0 tm 0 rpl tm 1c0 tm ? dh tm 3 dh simtoc : unused ? ?ead as 00 h : rese?ved ? cannot ?e changed special purpose data memory
rev. 1.00 30 ? ove ?? e ? ??? ? 01 ? rev. 1.00 31 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom special function register description most of the special function register details will be described in the relevant functional sections however several registers require a separate description in this section. indirect addressing registers C iar0, iar1, iar2 the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0, iar1 a nd iar2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from sector 0 while the iar1 register together with the mp1l/mp1h register pair and iar2 register together with the mp2l/mp2h register pair can access data from any data memory sector . as the indirec t addressing regi sters a re not physi cally i mplemented, rea ding t he indirec t addressing registers will return a result of "00h" and writing to the registers will result in no operation. memory pointers C mp0, mp1l, mp1h, mp2l, mp2h five memory pointers, known as mp0, mp1l, mp1h, mp2l, mp2h, are provided. these memory pointers are physically implemente d in the data memory and can be manipulated in the same way as n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. w hen a ny operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sectors according t o t he c orresponding mp1h or mp2h regi ster. di rect addre ssing c an be use d i n a ll sectors using the corresponding instruction which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example 1 data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue:
rev. 1.00 30 ?ove??e? ??? ?01? rev. 1.00 31 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom indirect addressing program example 2 data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a m ov a, 01h ; setup the memory sector m ov mp1h, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p1l, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar1 ; c lear t he d ata a t a ddress d efned b y m p1l inc m p1l ; i ncrement m emory po inter m p1l s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. direct addressing program example using extended instructions data .section data temp db ? code .section at 0 code org 00h start: l mov a, [m] ; move [m] data to acc l sub a, [m+1] ; compare [m] and [m+1] data s nz c ; [m]>[m+1]? j mp continue ; no l mov a, [m] ; yes, exchange [m] and [m+1] data m ov temp, a l mov a, [m+1] l mov [m], a m ov a, temp l mov [m+1], a continue: note: he re "m " i s a da ta m emory a ddress l ocated i n a ny da ta m emory se ctors. for e xample, m=1f0h, it indicates address 0f0h in sector 1. accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted.
rev. 1.00 3 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 33 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. t o is set by a wdt time-out. ? cz is the operational result of different fags for different instructions. refer to register defnitions for more details. ? sc is the result of the "xor" operation which is performed by the ov fag and the msb of the current instruction operation result.
rev. 1.00 3? ?ove??e? ??? ?01? rev. 1.00 33 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 ? a ? e sc cz to pdf ov z ac c r/w r/w r/w r r r/w r/w r/w r/w por x x 0 0 x x x x "x" unknown bit 7 sc : xor operation result - performed by the ov fag and the msb of the instruction operation result. bit 6 cz : operational result of different flags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/sbcm/lsbc/lsbcm instructions, the cz flag is the "and" operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected. bit 5 to : w atchdog t ime-out flag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow flag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 3 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 35 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom eeprom data memory this device contains an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8 bits for the device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and a data register in sector 0 and a single control register in sector 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in sector 1, can be read from or written to indirectly using the mp1l/mp1h or mp2l/mp2h memory pointer and indirect addressing register , iar1/iar2. because the eec control register is located at address 40h in sector 1, the mp1l or mp2l memory pointer must frst be set to the value 40h and the mp1h or mp2h memory pointer high byte set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea d5 d ? d3 d ? d1 d0 eed d7 d ? d5 d ? d3 d ? d1 d0 eec wre ? wr rde ? rd eeprom register list eea register bit 7 6 5 4 3 2 1 0 ? a ? e d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5~0 d5~d0 : data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.00 3? ?ove??e? ??? ?01? rev. 1.00 35 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom eed register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 ? a ? e wre ? wr rde ? rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the data eeprom w rite enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this is the data eeprom w rite control bit and when set high by the application program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this i s t he da ta e eprom re ad e nable bi t whi ch m ust be se t hi gh before da ta eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this i s t he da ta e eprom r ead c ontrol b it a nd wh en se t h igh b y t he a pplication program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden bit has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time.
rev. 1.00 3 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 37 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frst be cleared before implementing any write operat ions, and then set aga in aft er the write cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the memory pointer high byte register , mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operati on, ensuring that the w rite enable bit in the cont rol re gister is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.00 3? ?ove??e? ??? ?01? rev. 1.00 37 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the memory pointer high byte register , mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method 029 (( 3520b5(6 x vhu g hqhg dg guhvv 029 (( 029 v hwxs p hpru s rlqwhu 0 3/ 029 03/ 03/ s rlqwv w r ( (& u hjlvwhu 029 vh wxs p hpru s rlqwhu 0 3 029 03 6(7 ,5 v hw 5 (1 e lw h qdeoh u hdg r shudwlrqv 6(7,5 v wduw 5 hdg & foh v hw 5 e lw back: 6,5 f khf hdg f fh h g -03 . 5 ,5 g ldeh 3520 h dglh 5 03+ 02 h h dg g dd h lh 02 5b ? writing data to the eeprom C polling method 029 (( 3520b5(6 x vhu g hqhg dg guhvv 029 (( 029 ( (3520b7 x vhu g hqhg gd wd 029 (( 029 v hwxs p hpru s rlqwhu 0 3/ 029 03/ 03/ s rlqwv w r ( (& u hjlvwhu 029 vh wxs p hpru s rlqwhu 0 3 029 03 &/5 (0, 6(7 ,5 v hw : 5(1 e lw h qdeoh z ulwh r shudwlrqv 6(7 ,5 v wduw : ulwh & foh v hw : 5 e lw h [hfxwhg l pphgldwho d iwhu v hw : 5(1 e lw 6(7 ( 0, back: 6,5 f khf lh f fh h g -03 . 5 ,5 g ldeh 3520 h dglh 5 03+
rev. 1.00 38 ? ove ?? e ? ??? ? 01 ? rev. 1.00 39 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom oscillator s various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through confguration options and relevant control registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer and t ime base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast a nd sl ow sy stem c lock, t he d evice h as t he fe xibility t o o ptimize t he p erformance/power r atio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? nal c ? ystal hxt ? 00khz~1 ? mhz osc1/osc ? inte ? nal high speed rc hirc 8mhz exte ? nal low speed c ? ystal lxt 3 ? .7 ? 8khz xt1/xt ? inte ? nal low speed rc lirc 3 ? khz oscillator types system clock confgurations there are four methods of generating the system clock, two high speed oscillators and two low speed oscil lators. the high speed oscil lators are t he exte rnal crystal /ceramic oscil lator and the internal 8mhz rc oscillator . the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register a nd a s t he syste m c lock c an be dyna mically se lected. not e t hat t wo osc illator se lections must be made nam ely one hi gh speed and one low speed system oscil lators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. p?escale? f h high speed oscillato?s low speed oscillato?s f h /? f h /1? f h /?? f h /8 f h /? f h /3? hlclk? cks?~cks0 ?its f sys f sub hxt lirc hirc configu?ation options lxt fsubc fsub?~fsub0 ?its system clock confgurations
rev. 1.00 38 ?ove??e? ??? ?01? rev. 1.00 39 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom external high speed crystal oscillator C hxt the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. however , for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers speci fication. an additional confi guration option must be setup to confi gure the device according to whether the oscillator frequency is high, defned as equal to or above 1mhz, or low, which is defned as below 1mhz. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. ?ote: 1. r p is normally not required. c1 and c? are required. ?. although not shown osc1/osc? pins have a pa?asitic capacitance of a?ound 7pf. to inte?nal ci?cuits internal oscillator circuit c1 c? osc1 osc? r f r p crystal/resonator oscillator C hxt hxt oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0 pf 0 pf 8mhz 0 pf 0 pf ? mhz 0 pf 0 pf 1mhz 100 pf 100 pf ? 55khz ( ? ote ? ) 100 pf 100 pf ? ote: 1. c1 and c ? values a ? e fo ? guidance only. 2. hxt mode confguration option: 455khz. crystal recommended capacitor values internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as a f ixed f requency o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins.
rev. 1.00 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom external 32.768 khz crystal oscillator C lxt the e xternal 32.768 khz c rystal syst em osc illator i s one of t he l ow freque ncy osc illator c hoices, which is selected via the fsubc register. this clock source has a fxed frequency of 32.768 khz and requires a 32.768 khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768 khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compen sation due to dif ferent crystal manufacturing toleranc es. during power -up there is a time delay associated with the lxt oscillator waiting for it to start up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, indepen dent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be select ed in consultation with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, r p , is required. the fsubc regi ster det ermines i f t he xt 1/xt2 pi ns a re use d for t he lxt osc illator or a s i/ o or other pin-shared functional pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o or other pin-shared functional pins. ? if the lxt oscillator is used for any clock source, the 32.768 khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. ?ote: 1. r p ? c1 and c? are required. ?. although not shown xt1/xt? pins have a pa?asitic capacitance of a?ound 7pf. to inte?nal ci?cuits internal oscillator circuit c1 c? xt1 xt? r p 3?.7?8 khz inte?nal rc oscillato? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .7 ? 8khz 10 pf 10 pf ? ote: 1. c1 and c ? values a ? e fo ? guidance only. ? . r p =5m~10m is ? eco ?? ended. 32.768khz crystal recommended capacitor values
rev. 1.00 ?0 ?ove??e? ??? ?01? rev. 1.00 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the fsubc register. ? fsubc register bit 7 6 5 4 3 2 1 0 ? a ? e lxtlp fsub ? fsub5 fsub ? fsub3 fsub ? fsub1 fsub0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 1 0 1 0 bit 7 lxtlp : lxt low power control 0: quick start mode 1: low power mode bit 6~0 fsub6~fsub0 : f sub clock source selection 0101010: lirc 1010101: lxt other: mcu reset after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscilla tor start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the appli cation program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally , the only dif ference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via the fsubc register . it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%.
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce ve rsa, l ower spe ed c locks re duce current consumption. as both high and low speed clock sources are provided the means to switch between t hem dyna mically, t he use r c an opt imise t he ope ration of t heir m icrocontroller t o a chieve the best performance/power ratio. system clocks the device has dif ferent clock sources for both the cpu and peripheral function operation. by providing t he use r wi th a wi de range of cl ock se lections usi ng confgurat ion opt ions and regi ster programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is s elected us ing the the h lclk bit and ck s2~cks0 bits in the s mod register . the high speed system cloc k is sourced from an hxt or hirc oscillator . the low speed system clock source can be sourced from the internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillator , selected via confguring the fsub6~fsub0 bits in the fsubc register . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. p?escale? f h high speed oscillato?s low speed oscillato?s f h /? f h /1? f h /?? f h /8 f h /? f h /3? hlclk? cks?~cks0 ?its f sys f sub hxt lirc hirc configu?ation options lxt fsubc fsub?~fsub0 ?its wdt sleep ti?e base 0 ti?e base 1 tbck f tb f tbc f sys /? to pe?iphe?als device clock confgurations note : when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f sub f tbc ? ormal mode on f h ~f h / ?? on on slow mode on f sub on on idle0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillator . the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep0 mode is entered when an hal t instruction is executed and when the idlen bit in the smod registe r is low . in the sleep0 mode the cpu will be stopped, and the f sub clock will be stopped too, and the w atchdog t imer function is disabled. in this mode, the l vden must be set to "0". if the lvden is set ro "1", it wont enter sleep0 mode. sleep1 mode the sleep1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub clock will continue to operate if the lvden is "1" or the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped, the low frequency clock f sub will be on.
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the low frequency clock f sub will be on. note: if l vden=1 and the s leep or id le mode is entered, the l vd and bandgap functions will not be disabled, and the f sub clock will be forced to be enabked. in sleep mode, other peripheral will disable except wdt , lvd if enabled in sleep1. control registers a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 ? a ? e cks ? cks1 cks0 lto hto idle ? hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : the system clock selection when hlclk is "0" 000: f sub (f lxt or f lirc ) 001: f sub (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after a certain time if the hirc or hxt oscillator is used.
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub c lock wi ll be sel ected. w hen syst em c lock swi tches from t he fh clock to the f sub clock and the f h clock will be automatically switched of f to conserve power. ctrl register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 "x" unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as "0" bit 3 fsubf : fsubc control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the fsub6~fsub0 bits in the fsubc register contains any non- defned values. this bit can only be cleared to 0 by the application program. bit 2 lvrf : lvr function reset fag described eleswhere bit 1 lrf : lvr control register software reset fag described eleswhere bit 0 wrf : wdt control register software reset fag described eleswhere
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically al lowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when an hal t instructi on is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson bit in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal f sys =f h ~f h /?? f h on cpu ?un f sys on f tbc on f sub on idle1 halt inst?uction is executed cpu stop idle?=1 fsyso?=1 f sys on f tbc on f sub on idle0 halt inst?uction is executed cpu stop idle?=0 f sys off f tbc on f sub on slow f sys =f sub cpu ?un f sys on f tbc on f sub on f h off sleep1 halt inst?uction is executed f sys off cpu stop idle?=1 f tbc off f sub on wdt o? lvd on sleep0 halt inst?uction is executed f sys off cpu stop idle?=0 f tbc off f sub off wdt & lvd off
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. normal mode slow mode cks? ~ cks0 = 00xb & hlclk = 0 sleep0 mode wdt and lvd a?e all off idle? = 0 halt inst?uction is executed sleep1 mode halt inst?uction is executed idle0 mode idle?=1? fsyso?=0 halt inst?uction is executed idle1 mode idle?=1? fsyso?=1 halt inst?uction is executed wdt o? lvd is on idle? = 0
rev. 1.00 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "01 1", "100", "101", "1 10" or "111". a s a certain amount of time w ill be required for the high frequency clock to s tabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. normal mode slow mode cks?~cks0 000b? 001b as hlclk=0 o? hlclk=1 sleep0 mode wdt and lvd a?e all off idle?=0 halt inst?uction is executed sleep1 mode halt inst?uction is executed idle0 mode idle? =1? fsyso?=0 halt inst?uction is executed idle1 mode idle? =1? fsyso?=1 halt inst?uction is executed wdt o? lvd is on idle?=0 entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and l vd are both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.00 ?8 ?ove??e? ??? ?01? rev. 1.00 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or l vd is on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. if the wdt function is disabled, the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction, but the t ime base clock f tbc and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. if the wdt function is disabled, the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "hal t" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ctrl register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the system clock, t ime base clock f tbc and f sub clock will be on and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. if the wdt function is disabled, the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.00 50 ? ove ?? e ? ??? ? 01 ? rev. 1.00 51 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom standby current considerations as t he m ain re ason for e ntering t he sl eep or idl e mode i s t o ke ep t he c urrent c onsumption of the de vice t o a s l ow a va lue a s po ssible, pe rhaps on ly i n t he or der of se veral m icro-amps e xcept in t he i dle1 mod e, t here a re o ther c onsiderations wh ich m ust a lso b e t aken i nto a ccount b y t he circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or l ow l evel as a ny fl oating i nput pi ns c ould cre ate i nternal osc illations a nd result i n i ncreased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external ci rcuits t hat do not dra w current, such as other cmos inputs. al so note that addit ional standby current will also be required if the lxt or lirc oscillator has enabled. in the idle1 mode the system clock is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power - up or e xecuting t he c lear w atchdog t imer i nstructions a nd i s se t whe n e xecuting t he "hal t" instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "hal t" instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.00 50 ?ove??e? ??? ?01? rev. 1.00 51 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, du e to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f sub , the f sub clock is sourced from lirc or lxt oscillator select ed by the fsubc register . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the act ual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , temperat ure and process variations . the lxt oscillator is supplied by an external 32.768khz crystal. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable and reset mcu operation. wdtc register bit 7 6 5 4 3 2 1 0 ? a ? e we ? we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function software control 10101: disable 01010: enable others: reset mcu when these bits are changed by the environmental noise or software setting to reset the micro controller, the reset operat ion will be activated after a delay time, t sreset , and the wrf bit in the ctrl register will be set high. bit 2~0 ws2~ws0 : wdt t ime-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out perio d. ctrl register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 "x" unknown bit 7 fsyson : f sys control in idle mode described elsewhere bit 6~4 unimplemented, read as "0" bit 3 fsubf : fsubc control register software reset flag described elsew here
rev. 1.00 5 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 53 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 2 lvrf : lvr function reset flag described elsewhere bit 1 lrf : lvr control register software reset flag described elsewhere bit 0 wrf : wdt control register software reset flag 0: not occur 1: occurred this bit is set high by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to of fer the enable/disable control and reset control of the watchdog t imer. the wdt functio n will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after a delay time, t sreset . after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 10101b disa ? le 01010b ena ? le any othe ? values reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the w atchdog t imer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single "clr wdt" instruction to clear the wdt . the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 8ms for the 2 8 division ration . clr wdtinst?uction 8-stage divide? wdt p?escale? we?~we0 ?its wdtc registe? reset mcu lxt f sub f sub /? 8 8-to-1 mux clr ws?~ws0 (f sub /? 8 ~ f sub /? 18 ) wdt ti?e-out (? 8 /f sub ~ ? 18 /f sub ) lirc m u x fsubc fsub?~fsub0 ?its haltinst?uction watchdog timer
rev. 1.00 5? ?ove??e? ??? ?01? rev. 1.00 53 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , wil l be in a well -defined stat e and re ady to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the w atchdog t imer overfows and resets. all types of reset operations result in dif ferent register condition s being setup. another reset exists in the form of a low v oltage reset, l vr, where a ful l re set, i s i mplemented i n sit uations where t he power suppl y vol tage fa lls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur , through events occurring internally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. vdd powe?-on reset sst ti?e-out t rstd power-on reset timing chart low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set high. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specified by t lvr in the l vd/lvr electrical characteristics. if the low supply voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the l vs7~lvs0 bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by t he e nvironmental noi se or soft ware se tting, t he l vr wi ll reset t he de vice a fter a del ay time, t sreset . when this happens, the lrf bit in the ctrl register will be set high. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode.
rev. 1.00 5 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 55 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lvr inte?nal reset t rstd + t sst low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 ? a ? e lvs7 lvs ? lvs5 lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr v oltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be a ctivated a fter t he l ow vol tage c ondition ke eps m ore t han a t lvr t ime. in t his situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an m cu res et. the res et operation w ill be activated after a delay time, t sreset . however in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 "x" unknown bit 7 fsyson : f sys control in idle mode described elsewhere bit 6~4 unimplemented, read as "0" bit 3 fsubf : fsubc control register software reset flag described elsewhere bit 2 lvrf : lvr function reset flag 0: not occur 1: occurred this bit is set high when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 lrf : lvr control register software reset flag 0: not occur 1: occurred this bit is set high if the l vrc register contains any non-defned l vr voltage register values. this in ef fect acts like a software-reset function. this bit can only be cleared to zero by the application program. bit 0 wrf : wdt control register software reset fag described elsewhere
rev. 1.00 5? ?ove??e? ??? ?01? rev. 1.00 55 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as l vr reset except that the watchdog time-out fag t o will be set high. wdt ti?e-out inte?nal reset t rstd + t sst wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to zero and the t o fag will be set high. refer to the a.c. characteristics for t sst details. wdt ti?e-out inte?nal reset t sst wdt time-out reset during sleep or idle mode timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing ? ormal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing ? ormal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt ? ti ? e bases clea ? afte ? ? eset ? wdt ? egins counting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs stack pointe ? stack pointe ? will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes h ow e ach t ype o f re set a ffects e ach of t he m icrocontroller i nternal re gisters. not e t hat where m ore t han one pa ckage t ype e xists t he t able wi ll re fect t he sit uation for t he l arger pa ckage type.
rev. 1.00 5 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 57 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom register reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle/sleep) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp - - - x xxxx - - - u uuuu - - - u uuuu - - - u uuuu status xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu iar ? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp ? l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp ? h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu smod 000- 0011 000- 0011 000- 0011 uuu- uuuu tbc 0011 - 111 0011 - 111 0011 - 111 uuuu - uuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu lvdc - - 00 - 000 - - 00 - 000 - - 00 - 000 - - uu - uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu ctrl 0- - - 0x00 0- - - u1uu 0- - - uuuu 0- - - uuuu fsubc 0010 1010 0010 1010 0010 1010 uuuu uuuu i ? teg 0000 0000 0000 0000 0000 0000 uuuu uuuu i ? tc0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu i ? tc1 0000 0000 0000 0000 0000 0000 uuuu uuuu i ? tc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --00 --00 --uu --uu mfi ? --00 --00 --00 --00 --00 --00 --uu --uu mfi3 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu pb - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu pbc - - 11 1111 - - 11 1111 - - 11 1111 - - uu uuuu iohr0 0000 0000 0000 0000 0000 0000 uuuu uuuu iohr1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi ? 0000 0000 0000 0000 0000 0000 uuuu uuuu adrl xxxx - - - - xxxx - - - - xxxx - - - - uuuu - - - - (adrfs=0) uuuu uuuu (adrfs=1) adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu (adrfs=0) ---- uuuu (adrfs=1) adcr0 0110 0000 0110 0000 0110 0000 uuuu uuuu
rev. 1.00 5? ?ove??e? ??? ?01? rev. 1.00 57 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom register reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle/sleep) adcr1 00- 0 - 000 00- 0 - 000 00- 0 - 000 uu- u - uuu acerl 0000 0000 0000 0000 0000 0000 uuuu uuuu acerh ---- --00 ---- --00 ---- --00 ---- --uu tm0c0 0000 0- - - 0000 0- - - 0000 0- - - uuuu u- - - tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm0rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0rph ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu i ? tc3 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u eea - - 00 0000 - - 00 0000 - - 00 0000 - - uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmpc - - - 0 0000 - - - 0 0000 - - - 0 0000 - - - u uuuu tm ? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh ---- --00 ---- --00 ---- --00 ---- --uu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah ---- --00 ---- --00 ---- --00 ---- --uu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu lcdc0 xxxx - xxx xxxx - xxx xxxx - xxx uuuu - uuu lcdc1 xxx- xxxx xxx- xxxx xxx- xxxx uuu- uuuu segcr0 1111 1111 1111 1111 1111 1111 uuuu uuuu segcr1 1111 1111 1111 1111 1111 1111 uuuu uuuu segcr ? 1111 1111 1111 1111 1111 1111 uuuu uuuu segcr3 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu
rev. 1.00 58 ? ove ?? e ? ??? ? 01 ? rev. 1.00 59 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom register reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle/sleep) pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 - - - - 0000 - - - - 0000 - - - - uuuu - - - - pf 1111 - - - - 1111 - - - - 1111 - - - - uuuu - - - - pfc 1111 - - - - 1111 - - - - 1111 - - - - uuuu - - - - pgpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pg 1111 1111 1111 1111 1111 1111 uuuu uuuu pgc 1111 1111 1111 1111 1111 1111 uuuu uuuu simc0 111- 0000 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima 0000 0000 0000 0000 0000 0000 uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu simtoc 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.00 58 ?ove??e? ??? ?01? rev. 1.00 59 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom input/output ports the m icrocontrollers o ffer c onsiderable f lexibility o n t heir i /o p orts. w ith t he i nput o r o utput designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vice prov ides bi directional i nput/output l ines l abeled wi th por t na mes p a~pg. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa ? pa5 pa ? pa3 pa ? pa1 pa0 pac pac7 pac5 pac5 pac ? pac3 pac ? pac1 pac0 papu papu7 papu ? papu5 papu ? papu3 papu ? papu1 papu0 pawu pawu7 pawu ? pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 pb pb5 pb ? pb3 pb ? pb1 pb0 pbc pbc5 pbc ? pbc3 pbc ? pbc1 pbc0 pbpu pbpu5 pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 pc pc7 pc ? pc5 pc ? pc3 pc ? pc1 pc0 pcc pcc7 pcc ? pcc5 pcc ? pcc3 pcc ? pcc1 pcc0 pcpu pcpu7 pcpu ? pcpu5 pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 pd pd7 pd ? pd5 pd ? pd3 pd ? pd1 pd0 pdc pdc7 pdc ? pdc5 pdc ? pdc3 pdc ? pdc1 pdc0 pdpu pdpu7 pdpu ? pdpu5 pdpu ? pdpu3 pdpu ? pdpu1 pdpu0 pe pe7 pe ? pe5 pe ? pe3 pe ? pe1 pe0 pec pec7 pec ? pec5 pec ? pec3 pec ? pec1 pec0 pepu pepu7 pepu ? pepu5 pepu ? pepu3 pepu ? pepu1 pepu0 pf pf7 pf ? pf5 pf ? pfc pfc7 pfc ? pfc5 pfc ? pfpu pfpu7 pfpu ? pfpu5 pfpu ? pg pg7 pg ? pg5 pg ? pg3 pg ? pg1 pg0 pgc pgc7 pgc ? pgc5 pgc ? pgc3 pgc ? pgc1 pgc0 pgpu pgpu7 pgpu ? pgpu5 pgpu ? pgpu3 pgpu ? pgpu1 pgpu0 "" uni ? ple ? ented ? ? ead as "0" i/o logic function registers list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p apu~pgpu, a nd a re i mplemented usi ng we ak pmos transistors.
rev. 1.00 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pxpu register bit 7 6 5 4 3 2 1 0 ? a ? e pxpu7 pxpu ? pxpu5 pxpu ? pxpu3 pxpu ? pxpu1 pxpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pxpun : i/o port x pin pull-high function control 0: disable 1: enable the pxpun bit is used to control the pin pull-high function.here the "x" can be a, b, c, d, e, f and g. however, the actual available bits for each i/o port may be different. port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 ? a ? e pawu7 pawu ? pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pawun : port a pin w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its ow n control register known as p ac~pgc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pxc register bit 7 6 5 4 3 2 1 0 ? a ? e pxc7 pxc ? pxc5 pxc ? pxc3 pxc ? pxc1 pxc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pxcn : i/o port x pin t ype selection 0: output 1: input the pxcn bit is used to control the pin type selection. here the "x" can be a, b, c, d, e, f and g. however, the actual available bits for each i/o port may be different.
rev. 1.00 ?0 ?ove??e? ??? ?01? rev. 1.00 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established where more than one pin function is selected simultaneously. i/o pin structures the accompanyin g diagram illustrates the internal structures of the i/o logic function. as the exact logical cons truction of the i/o pin will dif fer from this diagram, it is supplied as a guide only to assist with the functional understanding of the logic function i/o pins. the wide range of pin-shared structures does not permit all types to be shown. m u x v dd cont?ol bit data bit data bus w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? syste? wake-up wake-up select i/o pin weak pull-up pull-high registe? select q d ck q d ck q q s s pa only logic function input/output structure programming considerations within the user program, one of the things frs t to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake- up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, generally abbrevia ted to the name tm. the tms are multi-purpose timi ng units and serve to provide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and periodic t ype tm sections. introduction the de vice c ontains fo ur t ms ha ving a re ference na me of t m0, t m1, t m2 a nd t m3. e ach individual t m can be categorized as a certain type, namely compact t ype t m or periodic t ype t m. although si milar i n n ature, t he d ifferent t m t ypes v ary i n t heir f eature c omplexity. t he c ommon features t o a ll of t he com pact a nd pe riodic t ype t ms wi ll be de scribed i n t his se ction a nd t he detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm ptm ti ? e ? /counte ? input captu ? e co ? pa ? e match output pwm channels 1 1 single pulse output 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm function summary this device contains a specifc number of either compact t ype and periodic t ype tm units which are shown in the table together with their individual reference names, tm0~tm3. tm0 tm1 tm2 tm3 10- ? it ptm 10- ? it ctm 10- ? it ctm 10- ? it ctm tm name/type reference tm operation the dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. w hen t he f ree r unning c ount-up c ounter h as t he sa me v alue a s t he p re-programmed comparator, known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable c lock source, which can be an internal clock or an external pin.
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f tbc clock source or the external tckn pin. the tckn pin cloc k source is used to allow an external signal to drive the tm as an external clock source for event counting. tm interrupts the compact t ype or periodic type t ms each has two internal interrupt, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the t ms, irrespective of what type, has one tm input pins, with the label tckn respectively. the tm input pin is essentially a clock source for the tm and is select ed using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an exter nal clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal t m i f se lected usi ng t he t nck2~tnck0 bi ts. the t m i nput pi n ca n be chose n t o have either a rising or falling active edge. the tms each have one or two output pins with the label tpn. when the tm is in the compare match output mode, t hese pins ca n be controll ed by the tm t o swi tch to a high or l ow l evel or to t oggle when a compare ma tch si tuation occurs. the exte rnal tpn out put pin is al so the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other functions, the tm output function must f rst be s etup us ing relavant regis ter. a s ingle bit in the regis ter determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is different, the details are provided in the accompanying table. periodic t ype tm output pin nam es ha ve a "_n" suf fix. pin nam es that include a "_0" or "_1" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complementary output pair, selected using the i/o register data bits. tm0 tm1 tm2 tm3 tp0_0 ? tp0_1 tp1 tp ? tp3 tm output pins
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register with a single bit in the register corresponding to a tm input/output pin. setting the bit correctly will setup the corresponding pin as a tm input/output if reset to zero the pin will retain its original other functions. tm0 (ptm) pa?/tp0_0 pa0/tck0 0 1 0 1 0 1 output captu?e input tck input pf7 output function t0cp1 t0cp1 pf7 pf7/tp0_1 0 1 0 1 pa? output function t0cp0 pa? 0 1 t0cp0 0 1 t0capts tm0 function pin control block diagram tm1 (ctm) pb3/tp1 t1cp pb3 output function 0 1 output pe?/tck1 tck input 0 1 pb3 tm1 function pin control block diagram
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tm2 (ctm) pb?/tp? t?cp pb? output function 0 1 output pe5/tck? tck input 0 1 pb? tm2 function pin control block diagram tm3 (ctm) pb1/tp3 t3cp pb1 output function 0 1 output pb0/tck3 tck input 0 1 pb1 tm3 function pin control block diagram tmpc register bit 7 6 5 4 3 2 1 0 ? a ? e t3cp t ? cp t1cp t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" bit 4 t3cp : tp3 pin control 0: disable 1: enable bit 3 t2cp : tp2 pin control 0: disable 1: enable bit 2 t1cp : tp1 pin control 0: disable 1: enable bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable
rev. 1.00 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the "mov" instruction to access the ccra and ccrp low byte registers, named tmnal and tmnrpl, using the following access procedures. accessing the ccra or ccrp low byte registers without following these access procedures will result in unpredictable values. data bus 8-?it buffe? tmndh tmndl tmnrph tmnrpl tmnah tmnal tm counte? registe? (read only) tm ccra registe? (read/w?ite) tm ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmnal or tmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmnah or tmnrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmndh, tmnah or tmnrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmndl, tmnal or tmnrpl C this step reads data from the 8-bit buffer.
rev. 1.00 ?? ?ove??e? ??? ?01? rev. 1.00 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom compact type tm C ctm the compact t ype tm contains three operating modes, which are compare match output, t imer/ event counter and pwm output modes. the compact t ype tm can also be controlled with an external input pin and can drive one external output pin. name tm no. tm input pin tm output pin 10- ? it ctm 1 ? ?? 3 tck1 ? tck ?? tck3 tp1 ? tp ?? tp3 f h f sys /? f h /?? f h /1? f tbc tckn 000 001 010 011 100 101 110 111 tnck?~tnck0 10-?it count-up counte? 3-?it co?pa?ato? p ccrp ?7~?9 ?0~?9 10-?it co?pa?ato? a tno? tnpau co?pa?ato? a match co?pa?ato? p match counte? clea? 0 1 output cont?ol pola?ity cont?ol tnoc tnm1? tnm0 tnio1? tnio0 tnaf inte??upt tnpf inte??upt tnpol ccra tncclr f tbc tpn pin output tpn compact type tm block diagram (n=1~3) compact type tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. there are also tw o internal comparators w ith the names , comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. t he ccrp is 3-bit wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources i ncluding a n i nput p in a nd c an a lso c ontrol a n o utput. al l o perating se tup c onditions a re selected using relevant internal registers. compact type tm register description overall operation of the compact t ype tm is controlled us ing a s eries of regis ters. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as three ccrp bits. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d ? d5 d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d ? d5 d ? d3 d ? d1 d0 tmnah d9 d8 10-bit compact type tm register list (n=1~3)
rev. 1.00 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 ?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 ? a ? e tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode or the pwm output mode then the tm output will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.00 ?8 ?ove??e? ??? ?01? rev. 1.00 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 ? a ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin state is undefned. bit 5~4 tnio1~tnio0 : select tpn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output when a compare match occurs. after the tmn output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tm is running.
rev. 1.00 70 ? ove ?? e ? ??? ? 01 ? rev. 1.00 71 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 3 tnoc : tmn output control bit compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output m ode it determines the logic level of the tm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tmn output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn output pin. when the bit is set high the tm output will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact type tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm output mode. tmndl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8
rev. 1.00 70 ?ove??e? ??? ?01? rev. 1.00 71 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tmnal register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm output mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as t he n ame o f t he m ode su ggests, a fter a c omparison i s m ade, t he t mn o utput p in wi ll c hange state. the tmn output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tmn output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 7 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 73 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tmn o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag ?ote tnio [1:0] = 10 active high output select he?e tnio [1:0] = 11 toggle output select output not affected ?y tnaf flag. re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol is high compare match output mode C tncclr=0 (n=1~3) note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tmn output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge
rev. 1.00 7? ?ove??e? ??? ?01? rev. 1.00 73 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra tno? tnpau tnpol tmn o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if tnoc=0 output toggle with tnaf flag ?ote tnio [1:0] = 10 active high output select he?e tnio [1:0] = 11 toggle output select output not affected ?y tnaf flag. re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change tncclr = 1; tnm [1:0] = 00 ccra int. flag tnaf ccrp int. flag tnpf compare match output mode C tncclr=1 (n=1~3) note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tmn output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. the tnpf fags is not generated when tncclr=1
rev. 1.00 7 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 75 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, hea ting cont rol, i llumination c ontrol et c. by providing a si gnal of fxe d frequenc y but of varying duty cycl e on the tm output, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. i n t he pw m ou tput mo de, t he t ncclr b it h as n o e ffect o n t he pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency o r d uty c ycle i s d etermined u sing t he t ndpx b it i n t he t mnc1 r egister. t he pw m waveform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he c cra a nd ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ctm, pwm output mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 5 ? 38 ? 51 ? ?? 0 7 ? 8 89 ? 10 ?? duty ccra if f sys =8mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the tm pwm output frequency=(f sys /4) / 512 =f sys /2048=3.90625 khz, duty=128 / 512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit ctm, pwm output mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra duty 1 ? 8 ? 5 ? 38 ? 51 ? ?? 0 7 ? 8 89 ? 10 ?? the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 7? ?ove??e? ??? ?01? rev. 1.00 75 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol tm o/p pin (tnoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o/p pin (tnoc=0) ccra int. flag tnaf ccrp int. flag tnpf tndpx = 0; tnm [1:0] = 10 pwm output mode C tndpx=0 (n=1~3) note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation.
rev. 1.00 7 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 77 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tmn o/p pin (tnoc=1) ti?e counte? clea?ed ?y ccra pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high pwm duty cycle set ?y ccrp pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tmn o/p pin (tnoc=0) tndpx = 1; tnm [1:0] = 10 pwm output mode C tndpx=1 (n=1~3) note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation.
rev. 1.00 7? ?ove??e? ??? ?01? rev. 1.00 77 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with external input pins and can drive external output pins. name tm no. tm input pin tm output pin 10- ? it ptm 0 tck0 ? tp0_0 ? tp0_1 tp0_0 ? tp0_1 tckn 10-?it count-up counte? 10-?it co?pa?ato? p ccrp 10-?it co?pa?ato? a output cont?ol pola?ity cont?ol tpn pin input/output tpn_0 ccra edge detecto? tpn_1 tncclr f h f sys /? f h /?? f h /1? f tbc tnck?~tnck0 tno? tnpau co?pa?ato? a match co?pa?ato? p match counte? clea? tnoc tnm1? tnm0 tnio1? tnio0 tnaf inte??upt tnpf inte??upt tnpol tnio1? tino0 f tbc tncapts 000 001 010 011 100 101 110 111 ?0~?9 ?0~?9 0 1 1 0 periodic type tm block diagram (n=0) periodic type tm operation the periodic t ype tm core is a 10-bit count-up counter which is driven by a user selectable internal or e xternal c lock sourc e. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 78 ? ove ?? e ? ??? ? 01 ? rev. 1.00 79 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom periodic type tm register description overall operation of the periodic t ype tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the int ernal 10-bit ccra val ue and ccrp val ue. the rem aining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck ? tnck1 tnck0 tno ? tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr tmndl d7 d ? d5 d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d ? d5 d ? d3 d ? d1 d0 tmnah d9 d8 tmnrpl d7 d ? d5 d ? d3 d ? d1 d0 tmnrph d9 d8 10-bit periodic tm register list (n=0) tmnc0 register bit 7 6 5 4 3 2 1 0 ? a ? e tnpau tnck ? tnck1 tnck0 tno ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retai n its residual value until the bit returns high again.
rev. 1.00 78 ?ove??e? ??? ?01? rev. 1.00 79 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom if the tm is in the compare match output mode, pwm output mode or single pulse output mode then the tm output pin will be reset to its initial conditi on, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as "0" tmnc1 register bit 7 6 5 4 3 2 1 0 ? a ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1 or tckn 01: input capture at falling edge of tpn_0, tpn_1 or tckn 10: input capture at falling/rising edge of tpn_0, tpn_1 or tckn 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tm is running.
rev. 1.00 80 ? ove ?? e ? ??? ? 01 ? rev. 1.00 81 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm output mode it determines if t he pw m si gnal i s a ctive hi gh or a ctive l ow. in t he si ngle pul se out put mode i t determines the logic level of the tm output pin when the tnon bit changes from low to high. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0, tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tncapts : tmn capture t rigger source selection 0: from tpn_0, tpn_1 pin 1: from tck0 pin bit 0 tncclr : select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm output mode, single pulse output or capture input mode. tmndl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8
rev. 1.00 80 ?ove??e? ??? ?01? rev. 1.00 81 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tmnal register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnrpl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn ccrp low byte register bit 7 ~ bit 0 tmn 10-bit ccrp bit 7 ~ bit 0 tmnrph register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : tmn ccrp high byte register bit 1 ~ bit 0 tmn 10-bit ccrp bit 9 ~ bit 8
rev. 1.00 8 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 83 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom periodic type tm operating modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be cleared to zero. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 8? ?ove??e? ??? ?01? rev. 1.00 83 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t output pin set to initial level low if tnoc=0 output toggle with tnaf flag ?ote tnio [1:0] = 10 active high output select he?e tnio [1:0] = 11 toggle output select output not affected ?y tnaf flag. re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol is high tncclr = 0; tnm [1:0] = 00 compare match output mode C tncclr=0 (n=0) note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.00 8 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 85 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if tnoc=0 output toggle with tnaf flag ?ote tnio [1:0] = 10 active high output select he?e tnio [1:0] = 11 toggle output select output not affected ?y tnaf flag. re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change tncclr = 1; tnm [1:0] = 00 compare match output mode C tncclr=1 (n=0) note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
rev. 1.00 8? ?ove??e? ??? ?01? rev. 1.00 85 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. i n t he pw m ou tput mo de, t he t ncclr b it h as n o e ffect o n t he pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm output mode , edge-aligned mode ccrp 1~1023 0 pe ? iod 1~10 ? 3 10 ?? duty ccra if f sys =8mhz, tm clock source select f sys /4, ccrp=512 and ccra=128, the tm pwm output frequency=(f sys /4)/512=f sys /2048=3.90625khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 8 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 87 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o/p pin (tnoc=0) tnm [1:0] = 10 pwm output mode (n=0) note: 1. counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 8? ?ove??e? ??? ?01? rev. 1.00 87 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom single pulse output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the t rigger fo r t he pu lse ou tput l eading e dge i s a l ow t o hi gh t ransition of t he t non bi t, whi ch can be implement ed using the appli cation program. however in the single pulse output mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control t he p ulse wi dth. a c ompare m atch f rom c omparator a wi ll a lso g enerate a t m i nterrupt. the counter can only be reset back to zero when the tnon bit change s from low to high when the counter restarts. in the single pulse output mode ccrp is not used. the tncclr bit is not used in this mode. tno? ?it 0 1 s/w co??and settno? o? tckn pin t?ansition tno? ?it 1 0 ccra t?ailing edge s/w co??and clrtno? o? ccra co?pa?e match tpn output pin pulse width = ccra value ccra leading edge single pulse generation (n=0)
rev. 1.00 88 ? ove ?? e ? ??? ? 01 ? rev. 1.00 89 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tn o? ?etu?ns high pulse width set ?y ccra output inve?ts when tnpol = 1 ?o ccrp inte??upts gene?ated tm o/p pin (tnoc=0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?atch tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnm [1:0] = 10 ; tnio [1:0] = 11 single pulse output mode (n=0) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse output mode, tnio[1:0] must be set to "11" and cannot be changed.
rev. 1.00 88 ?ove??e? ??? ?01? rev. 1.00 89 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn_0, tpn_1 or tckn pin which is selected using the tncapts bit in the tmnc1 register. t he i nput p in a ctive e dge c an b e e ither a r ising e dge, a f alling e dge o r b oth r ising a nd f alling edges; t he a ctive e dge t ransition t ype i s se lected usi ng t he t nio1 a nd t nio0 bi ts i n t he t mnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0, tpn_1 or tckn pin the present value in the c ounter wi ll be l atched i nto t he ccra re gisters a nd a t m i nterrupt ge nerated. irrespec tive of what events occur on the tpn_0, tpn_1 or tckn pin, the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse wi dths. the tnio1 and tnio0 bit s ca n se lect the ac tive tri gger edge on the tpn_0, tpn_1 or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0, tpn_1 or tckn pin, however it must be noted that the counter will continue to run. as the tpn_0, tpn_1 or tckn pin is pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode.
rev. 1.00 90 ? ove ?? e ? ??? ? 01 ? rev. 1.00 91 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom counte? value yy ccrp tno? tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value ti?e counte? clea?ed ?y ccrp pause resu?e counte? reset tnm[1:0] = 01 tm captu?e pin tpn_x o? tckn xx counte? stop tnio [1:0] value active edge active edge active edge 00 - rising edge 01 - falling edge 10 - both edges 11 - disa?le captu?e xx yy xx yy capture input mode note: 1. tnm[1:0]=01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 90 ?ove??e? ??? ?01? rev. 1.00 91 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom analog to digital converter C adc the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d converter overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. input channels a/d channel select bits input pins 10 acs ?? acs3~acs0 a ? 0~a ? 9 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. ace9~ace0 a/d conve?te? start eocb adoff v ss a/d clock ? ? (?=0~?) f sys adck?~adck0 v dd adoff bit adrl adrh pb0/a?0 pb1/a?1 a/d data registe?s adrfs pb?/vref vrefs bit v bg vbge? a/d refe?ence voltage acs?~acs0 pb?/a?? pb3/a?3 pe?/a?? pe5/a?5 pe?/a?? pb?/a?7 pe7/a?8 pb5/a?9 a/d converter structure a/d converter register description overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining four registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl (adrfs=0) d3 d ? d1 d0 adrl (adrfs=1) d7 d ? d5 d ? d3 d ? d1 d0 adrh (adrfs=0) d11 d10 d9 d8 d7 d ? d5 d ? adrh (adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs3 acs ? acs1 acs0 adcr1 acs ? vbge ? vrefs adck ? adck1 adck0 acerl ace7 ace ? ace5 ace ? ace3 ace ? ace1 ace0 acerh ace9 ace8 a/d converter register list
rev. 1.00 9 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 93 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom a/d converter data register C adrl, adrh the de vice, whi ch ha s a n i nternal 12 -bit a/ d c onverter, re quires t wo da ta re gisters, a hi gh by te register, kn own a s adrh, a nd a l ow by te r egister, k nown a s adrl . aft er t he c onversion pr ocess takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised , the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d5 d ? d3 d ? d1 d0 1 d11 d10 d9 d8 d7 d ? d5 d ? d3 d ? d1 d0 a/d converter data registers a/d converter control registers C adcr0, adcr1, acerl, acerh to control the function and operatio n of the a/d converter , four control registers known as adcr0, adcr1, ace rl a nd ace rh a re provi ded. t hese 8-bi t re gisters de fine func tions such a s t he selection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d converter clock source as well as controlling the start function and monitoring the end of a/d conversion status. the acs3~acs0 bits in the adcr0 register and the acs4 bit in the adcr1 register defne the a/d converter input channel number . as the device contains only one actual a nalog t o d igital c onverter h ardware c ircuit, e ach o f t he i ndividual a nalog i nputs m ust b e routed to the converter . it is the function of the acs4~acs0 bits to determine which analog channel input pin or internal v bg is actually connected to the internal a/d converter. the acerh and acerl control re gisters cont ain the ace9~ace0 bi ts whi ch de termine whi ch pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d converter input function, cle aring the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in additio n, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. ? adcr0 register bit 7 6 5 4 3 2 1 0 ? a ? e start eocb adoff adrfs acs3 acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to "1" this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high.
rev. 1.00 9? ?ove??e? ??? ?01? rev. 1.00 93 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 5 adoff : a/d converter module power on/off control bit 0: a/d converter module power on 1: a/d converter module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the a/d converter module. bit 4 adrfs : a/d data format control bit 0: a/d converter data msb is adrh bit 7, lsb is adrl bit 4 1: a/d converter data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3~acs0 : select a/d channel (when acs4 is "0") 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001~1111: an9 these are the a/d channel select control bits. as there is only one internal hardware a/ d converter each of the ten a/d inputs must be routed to the internal converter using these bits. if the acs4 bit is set high, then the internal bandgap v bg will be routed to the a/d converter. ? adcr1 register bit 7 6 5 4 3 2 1 0 ? a ? e acs ? vbge ? vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal v bg as a/d converter input control 0: disable 1: enable this bi t e nables v bg t o be c onnected t o t he a/ d c onverter. t he vbge n bi t m ust frst have been set to enable the bandgap circuit v bg voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap v bg voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 vbgen : internal v bg control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap voltage v bg can be used by the a/d converter . if v bg is not used by the a/d convert er and the l vr/lvd function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when v bg is switched on for use by the a/d converter , a time t bgs should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0"
rev. 1.00 9 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 95 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 4 vrefs : select a/d converter reference voltage 0: internal a/d converter power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. when the a/d converter reference voltage is supplied on the external vref pin which is pin-shared with other functions, all of the pin-shared function s except vref on this pin are disabled. bit 3 unimplemented, read as "0" bit 2~0 adck2~adck0 : select a/d converter clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. ? bandgap reference voltage on/off true table: acs4 vbgen lvr/lvd v bg bandgap reference voltage x 0 ena ? le off to g ? d on x 0 disa ? le off to g ? d off x 1 x on on x: dont ca ? e ? acerl register bit 7 6 5 4 3 2 1 0 ? a ? e ace7 ace ? ace5 ace ? ace3 ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ace7 : defne pb4 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pe6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pe5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pe4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pb1 is a/d input or not 0: not a/d inp ut 1: a/d input, an1 bit 0 ace0 : defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an 0
rev. 1.00 9? ?ove??e? ??? ?01? rev. 1.00 95 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ? acerl register bit 7 6 5 4 3 2 1 0 ? a ? e ace9 ace8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1 ace9 : defne pb5 is a/d input or not 0: not a/d input 1: a/d input, an9 bit 0 ace8 : defne pe7 is a/d input or not 0: not a/d input 1: a/d input, an8 a/d converter operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be beyond the specifed a/d clock period range.
rev. 1.00 9 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 97 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom f sys a/d clock period (t adck ) adck [2:0]=000 (f sys ) adck [2:0]=001 (f sys /2) adck [2:0]=010 (f sys /4) adck [2:0]=011 (f sys /8) adck [2:0]=100 (f sys /16) adck [2:0]=101 (f sys /32) adck [2:0]=110 (f sys /64) adck [2:0]=111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned ? mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned ? mhz ? 50ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s 2s 4s 8s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace9~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. a/d converter reference voltage the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d converter input signals all of the a /d analog input pins are pin-shared w ith the i/o pins as w ell as other functions . the ace9~ace0 bits in the acerh and acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace9~ace0 bits for its corresponding pin is set high then the pins will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the ace9~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref . however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
rev. 1.00 9? ?ove??e? ??? ?01? rev. 1.00 97 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom
? ? ? ? ?? ? a/d input structure conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversion. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate=a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. adc module o? start eocb acs?~acs0 ?its off on off on t o??st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e t adc a/d conve?sion ti?e t adc a/d conve?sion ti?e 011b 010b 000b 001b 1: define po?t configu?ation ?: select analog channel adoff powe?-on reset reset a/d conve?te? sta?t of a/d conve?sion end of a/d conve?sion reset a/d conve?te? sta?t of a/d conve?sion end of a/d conve?sion reset a/d conve?te? sta?t of a/d conve?sion a/d conversion timing
rev. 1.00 98 ? ove ?? e ? ??? ? 01 ? rev. 1.00 99 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace9~ace0 bits in the acerh and acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? ste p 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the met hod of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted.
rev. 1.00 98 ?ove??e? ??? ?01? rev. 1.00 99 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d conversion function as the device contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the actual a/d converter reference voltage, v ref voltage, this gives a single bit analog input value of v ref divided by 4096. 1 lsb=v ref /4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital valuev ref /4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v ref level. note that here the v ref voltage is the actual a/d converter reference voltage determined by the vrefs bit. fffh ffeh ffdh 03h 0?h 01h 0 1 ? 3 ?093 ?09? ?095 ?09? v ref ?09? analog input voltage a/d conversion result 1.5 lsb 0.5 lsb ideal a/d conversion function
rev. 1.00 100 ? ove ?? e ? ??? ? 01 ? rev. 1.00 101 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom a/d conversion programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; d isable a /d c onverter i nterrupt mov a , 03h mov adcr1, a ; s elect f sys /8 as a /d c lock a nd s witch o ff v bg clr adoff mov a, 0 fh ; s etup ac erl t o c onfgure p ins a n0~an3 mov acerl, a mov a , 00h mov acerh, a mov a , 00h mov adcr0, a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : : start_conversion: clr start set start ; r eset a /d clr start ; s tart a /d polling_eoc: sz eocb ; p oll t he a dcr0 r egister e ocb b it t o d etect e nd o f a /d c onversion jmp polling_eoc ; c ontinue p olling mov a, a drl ; re ad l ow b yte c onversion re sult v alue mov adrl_buffer, a ; s ave r esult t o us er d efned r egister mov a, a drh ; re ad h igh b yte c onversion re sult v alue mov adrh_buffer, a ; s ave r esult t o us er d efned r egister : jmp start_conversion ; s tart n ext a/ d c onversion note: t o power off the a/d converter, it is necessary to set adoff as "1".
rev. 1.00 100 ?ove??e? ??? ?01? rev. 1.00 101 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom example: using the interrupt method to detect the end of conversion clr ade ; d isable a /d c onverter i nterrupt mov a , 03h mov adcr1, a ; s elect f sys /8 as a /d c lock a nd s witch o ff v bg clr adoff mov a, 0 fh ; s etup ac erl t o c onfgure p ins a n0~an3 mov acerl, a mov a , 00h mov acerh, a mov a , 00h mov adcr0, a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : : start_conversion: clr start set start ; r eset a /d clr start ; s tart a /d clr adf ; c lear a /d c onverter i nterrupt re quest f ag set ade ; e nable a /d c onverter i nterrupt set emi ; e nable gl obal i nterrupt : : ; a /d c onverter i nterrupt s ervice ro utine adc_isr: mov acc_stack, a ; s ave a cc t o u ser d efned m emory mov a, s tatus mov status_stack, a ; s ave st atus t o us er d efned m emory : : mov a, a drl ; re ad l ow b yte c onversion re sult v alue mov adrl_buffer, a ; s ave r esult t o us er d efned r egister mov a, a drh ; re ad h igh b yte c onversion re sult v alue mov adrh_buffer, a ; s ave r esult t o us er d efned r egister : : exit_isr: mov a, s tatus_stack mov status, a ; restore s tatus f rom u ser d efned m emory mov a, ac c_stack ; r estore a cc fr om u ser d efned m emory clr adf ; c lear a /d c onverter i nterrupt f ag reti note: t o power off the a/d converter, it is necessary to set adoff as "1".
rev. 1.00 10 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 103 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom serial interface module C sim the device contai ns a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash memory , etc. as both interf ace types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash memory devices etc. originally developed by motorola, the four line spi interface is a synchronous seri al data interface that has a relatively simple communicat ion prot ocol simplifyi ng the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a si ngle m aster, but t his de vice i s provi ded onl y one scs pi n. if t he m aster ne eds t o c ontrol multiple slave devices from a single master, the master can use i/o pin to select the slave devices. sck spi maste? sdo sdi scs sck spi slave sdo sdi scs spi master/slave connection spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines; sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by setting the correct bits in the simc0 and simc2 registers. the spi can be disabled or enabled using the simen bit in the simc0 register . communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master . the master also controls the clock signal. as the devic e only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable pin function, set csen bit to "0" the scs pin will be foating state.
rev. 1.00 10? ?ove??e? ??? ?01? rev. 1.00 103 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom simd tx/rx shift registe? sdi pin clock edge/pola?ity cont?ol ckeg ckpolb clock sou?ce select f sys f sub tm0 ccrp match frequency/2 sck pin cse? busy status sdo pin wcol trf scs pin data bus simicf spi block diagram the spi function in the device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdeb1 simdeb0 sime ? simicf simd d7 d ? d5 d ? d3 d ? d1 d0 simc ? d7 d ? ckpolb ckeg mls cse ? wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register.
rev. 1.00 10 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 105 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ? simd register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function a nd t o se t t he da ta t ransmission c lock fre quency. al though not c onnected wi th t he spi function, the simc0 register is also used to control the peripheral clock prescaler . register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. ? simc0 register bit 7 6 5 4 3 2 1 0 ? a ? e sim ? sim1 sim0 simdeb1 simdeb0 sime ? simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if t he i 2 c or spi func tion, t hey a re used t o c ontrol t he spi ma ster/slave sel ection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0 or f sub . if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb[1:0] : i 2 c debounce t ime selection the simdeb[1:0] bits are of no use in spi mode of sim, please ignore these selection bits when operate in spi mode. bit 1 simen : sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states.
rev. 1.00 10? ?ove??e? ??? ?01? rev. 1.00 105 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 0 simicf : sim spi incomplete flag 0: sim spi incompleted is not occurred 1: sim spi incompleted is occurred this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operate s in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 togethe r with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program. ? simc2 register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? ckpolb ckeg mls cse ? wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 d7~d6 : undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge t ype ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin.
rev. 1.00 10 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 107 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 1 wcol : spi w rite collision flag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi t ransmit/receive complete flag 0: data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set high automatically when an spi da ta t ransmission i s c ompleted, but m ust c leared t o z ero by t he a pplication program. it can be used to generate an interrupt. spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi wil l c ontinue t o funct ion i n spe cial idl e mode s i f t he c lock sourc e use d by t he spi interface is still active. sck (ckpolb=1? ckeg=0) sck (ckpolb=0? ckeg=0) sck (ckpolb=1? ckeg=1) sck (ckpolb=0? ckeg=1) scs sdo (ckeg=0) sdo (ckeg=1) sdi data captu?e w?ite to simd sime?? cse?=1 sime?=1? cse?=0 (exte?nal pull-high) d7/d0 d ? /d1 d5/d? d? /d3 d3/d? d? /d5 d1/d? d0/d7 d7/d0 d ? /d1 d5/d? d? /d3 d3/d? d? /d5 d1/d? d0/d7 spi master mode timing
rev. 1.00 10? ?ove??e? ??? ?01? rev. 1.00 107 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e w?ite to simd (sdo does not change until fi?st sck edge) d7/d0 d ? /d1 d5/d? d? /d3 d3/d? d? /d5 d1/d? d0/d7 spi slave mode timing C ckeg=0 sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data captu?e d7/d0 d ? /d1 d5/d? d? /d3 d3/d? d? /d5 d1/d? d0/d7 w?ite to simd (sdo changes as soon as w?iting occu?s; sdo is floating if scs=1) ?ote: fo? spi slave ?ode? if sime?=1 and cse?=0? spi is always ena?led and igno?es the scs level. spi slave mode ti?ing C ckeg=1
rev. 1.00 108 ? ove ?? e ? ??? ? 01 ? rev. 1.00 109 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom clea? wcol w?ite data into simd wcol=1? t?ans?ission co?pleted? (trf=1?) read data f?o? simd clea? trf e?d t?ansfe? finished? a spi t?ansfe? maste? o? slave ? sime?=1 configu?e ckpolb? ckeg? cse? and mls a sim[?:0]=000? 001? 010? 011 o? 100 sim[?:0]=101 maste? slave y y ? ? ? y spi transfer control flowchart
rev. 1.00 108 ?ove??e? ??? ?01? rev. 1.00 109 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom spi bus enable/disable to enable the spi bus, set csen=1 and scs =0, then wait for data to be written into the simd (txrx buf fer) re gister. for t he ma ster mode , a fter da ta ha s be en wri tten t o t he simd (t xrx buffer) register , then transmission or reception will start automatically . when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. when the spi bus is disabled, sck, sdi, sdo and scs can become i/o pins or other pin-shared functions using the corresponding pin-shared control bits. spi operation all communication is carried out using the 4-line interface for either master or slave mode. the csen bit in the simc2 register controls the overall function of the spi interface. setting this bit high will enable the spi interfac e by allowing the scs line to be active, which can then be used to control the spi interface. if the csen bit is low , the spi interface will be disabled and the scs line will be in a foating condition and can therefore not be used for control of the spi interface. if the csen bit and the simen bit in the simc0 are set high, thi s will place the sdi line in a foating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity selection bit ckpolb in the simc2 register . if in slave mode the sck line will be in a foating condition. if the simen bit is low , then the bus will be disabled and scs , sdi, sdo and sck will all become i/o pins or the other functions using the corresponding pin-shared control bits . in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the simd register . in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode . ? master mode: ? step 1 select the spi master mode and clock source using the sim2~sim0 bits in the simc0 control register . ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the slave devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register , which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this, go to step5. for r ead o perations: t he d ata t ransferred i n o n t he sdi l ine wi ll b e st ored i n t he t xrx b uffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register.
rev. 1.00 110 ? ove ?? e ? ??? ? 01 ? rev. 1.00 111 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ? step 8 clear trf . ? step 9 go to step 4. ? slave mode: ? step 1 select the spi slave mode using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the master devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register , which will actually place the data into the txrx buffer. then wait for the master clock sck and scs signal. after this, go to step5. for r ead o perations: t he d ata t ransferred i n o n t he sdi l ine wi ll b e st ored i n t he t xrx b uffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf . ? step 9 go to step 4. error detection the wcol bit in the simc2 register is provided to indicate errors during data transfer . the bit is set by the spi serial interface but must be cleared by the application program. this bit indicates a data colli sion has occurred which happens if a write to the simd register takes place during a data transfer operation and will prevent the write operation from continuing.
rev. 1.00 110 ?ove??e? ??? ?01? rev. 1.00 111 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom i 2 c interface the i 2 c i nterface i s use d t o c ommunicate wi th e xternal pe ripheral de vices suc h a s se nsors e tc. originally de veloped by phi lips, i t i s a t wo l ine l ow spe ed se rial i nterface for sync hronous se rial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. device slave device maste? device slave vdd sda scl i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data; however, it is the master device that has overall control of the bus. for the device, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the pull-up control function pin-shared with scl/sda pin is still applicable even if i 2 c device is activ ated and the related internal pull-up register could be controlled by its corresponding pull-up control register. shift registe? t?ans?it/ receive cont?ol unit f sys f sub data bus i ? c add?ess registe? (sima) i ? c data registe? (simd) add?ess co?pa?ato? read/w?ite slave srw detect sta?t o? stop hbb ti?e-out cont?ol simtof add?ess matchChaas i ? c inte??upt de?ounce ci?cuit?y scl pin m u x txak data out msb simtoe? add?ess match simdeb[1:0] sda pin data in msb di?ection cont?ol htx 8-?it data t?ansfe? co?pleteChcf i 2 c block diagram
rev. 1.00 11 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 113 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom start signal f?o? maste? send slave add?ess and r/w ?it f?o? maste? acknowledge f?o? slave send data ?yte f?o? maste? acknowledge f?o? slave stop signal f?o? maste? the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the internal clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) ? o de ? ounce f sys > ? mhz f sys > 5 mhz ? syste ? clock de ? ounce f sys > ? mhz f sys > 10 mhz ? syste ? clock de ? ounce f sys > 8 mhz f sys > ? 0 mhz i 2 c minimum f sys frequency i 2 c registers there a re t hree c ontrol re gisters a ssociated wi th t he i 2 c bus, simc0, simc1 a nd simt oc, one address register , sima and one data register , simd. the simd register , which is shown in the above spi section , is also used to store the data being transmitted and received on the i 2 c bus. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. the simt oc register is used for i 2 c time-out control. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdeb1 simdeb0 sime ? simicf simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d ? d5 d ? d3 d ? d1 d0 sima a ? a5 a ? a3 a ? a1 a0 d0 simtoc simtoe ? simtof simtos5 simtos ? simtos3 simtos ? simtos1 simtos0 i 2 c register list
rev. 1.00 11 ? ?ove??e? ??? ?01? rev. 1.00 113 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ? simc0 register bit 7 6 5 4 3 2 1 0 ? a ? e sim ? sim1 sim0 simdeb1 simdeb0 sime ? simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if t he i 2 c or spi func tion, t hey a re used t o c ontrol t he spi ma ster/slave sel ection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0 or f sub . if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as "0" bit 3~2 simdeb1~simdeb0 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and shoul d therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim spi incomplete flag simicf is of no use in i 2 c mode of sim, please ignore this fag when operate in i 2 c mode. ? simc1 register bit 7 6 5 4 3 2 1 0 ? a ? e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data t ransfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
rev. 1.00 11 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 115 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 6 haas : i 2 c bus address match flag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy flag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fag is the i 2 c busy fag. t his fag will be "1" when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be cleared to zero when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is t ransmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus t ransmit acknowledge flag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bit of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match w ake up function control 0: disable 1: enable. this bit should be set to 1 to enabl e the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correct device operation. bit 0 rxak : i 2 c bus receive acknowledge flag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the r xak f lag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s "0 ", i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receive wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus.
rev. 1.00 11 ? ?ove??e? ??? ?01? rev. 1.00 115 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functio ns. before the device write data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown ? sima register bit 7 6 5 4 3 2 1 0 ? a ? e a ? a5 a ? a3 a ? a1 a0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 a6~a0 : i 2 c slave address a6~a0 is the i 2 c slave address bit 6 ~ bit 0. the si ma r egister i s a lso u sed b y t he spi i nterface b ut h as t he n ame si mc2. t he sima register is the location where the 7-bit slave address of the slave device is stored. bit 7~bit 1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 d0 : undefned bit this bit can be read or written by user software program. ? simtoc register bit 7 6 5 4 3 2 1 0 ? a ? e simtoe ? simtof simtos5 simtos ? simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simtoen : i 2 c interface t ime-out control 0: disable 1: enable bit 6 simtof : i 2 c interface t ime-out fag 0: no occurred 1: occurred the simt of fag is set by the time-out circuitry when the time-out event occurs and cleared by software program. bit 5~0 simtos5~simtos0 : i 2 c interface t ime-out period selection the i 2 c t ime-out clock source is f sub /32. the i 2 c t ime-out time is ([simtos5:simtos0] + 1) (32/f sub )
rev. 1.00 11 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 117 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave devi ce must frst check the condition of the haas bit and simt of bit to determ ine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer or from the i 2 c communication time-out. during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/ write bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 bits to "1 10" and the simen bits to "1" in the simc0 register to enable the i 2 c bus. ? step 2 write the slave address to the i 2 c bus address register sima. ? step 3 set the interrupt enable bit sime to enable the sim interrupt. set sim[?:0]=110 set sime? w?ite slave add?ess to sima i ? c bus inte??upt=? clr sime poll simf to decide when to go to i ? c bus isr ?o yes set sime wait fo? inte??upt goto main p?og?a? goto main p?og?a? sta?t i 2 c bus initialisation flow chart
rev. 1.00 11 ? ?ove??e? ??? ?01? rev. 1.00 117 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas bit and simt of bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or from the i 2 c comm unication time-out. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 register defnes whether the master device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set high. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be cleared to zero.
rev. 1.00 118 ? ove ?? e ? ??? ? 01 ? rev. 1.00 119 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom i 2 c bus data and acknowledge signal the transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt o f 8 -bit o f d ata, t he r eceiver m ust t ransmit a n a cknowledge si gnal, l evel "0 ", b efore i t c an receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receive r, then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register . if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver , the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. sta?t scl sda scl sda 1 s=sta?t (1 ?it) sa=slave add?ess (7 ?its) sr=srw ?it (1 ?it) m=slave device send acknowledge ?it (1 ?it) d=data (8 ?its) a=ack (rxak ?it fo? t?ans?itte?? txak ?it fo? ?eceive?? 1 ?it) p=stop (1 ?it) 0 ack slave add?ess srw stop data ack 1 1 0 1 0 1 0 1 0 0 1 0 1 0 0 s sa sr m d a d a s sa sr m d a d a p i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.00 118 ?ove??e? ??? ?01? rev. 1.00 119 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom sta?t simtof=1? set simtoe? clr simtof reti haas=1? htx=1? srw=1? read f?o? simd to ?elease scl line reti rxak=1? w?ite data to simd to ?elease scl line clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti reti set htx w?ite data to simd to ?elease scl line reti clr htx clr txak du??y ?ead f?o? simd to ?elease scl line reti yes ?o ?o yes yes ?o yes ?o ?o yes i 2 c bus isr flow chart
rev. 1.00 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom i 2 c time-out function in order to reduce the i 2 c lockup problem due to reception of erroneous clock s ources, a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and the simc1 register will be reset, the simt of bit in the simt oc register will be set high after a certain time-out period. the t ime out function enable/disable and the time-out period are managed by the simtoc register. i 2 c time out operation the time-out counter starts to count on an i 2 c bus "st art" & "address match" condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater t han t he t ime-out p eriod sp ecifed b y t he si mtoc r egister, t hen a t ime-out c ondition wi ll occur. the time-out function will stop when an i 2 c "st op" condition occurs. there are 64 time-out period selections which can be selected using the simtos0~simtos5 bits in the simtoc register. sta?t scl sda scl sda 1 0 ack slave add?ess srw stop 1101010 10010100 i ? c ti?e-out counte? sta?t i ? c ti?e-out counte? ?eset on scl negative t?ansition i 2 c time-out diagram when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be c leared t o z ero a nd t he simt of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: registers after i 2 c time-out simd ? sima ? simc0 ? o change simc1 reset to por condition i 2 c registers after time-out
rev. 1.00 1?0 ?ove??e? ??? ?01? rev. 1.00 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lcd display memory the device provides an area of embedded data memory for lcd display . this area is located from 80h to 9fh of the ram at sector 1. the memory pointer mp1h is the switch between the ram and the lcd display memory . when the mp1h=01h, data written into 80h~9fh will af fect the lcd display. when the mp1h is written with values other than 01h, any data written into 80h~9fh is meant to access the general purpose data memory. the lcd display memory can be read and written to by indirect addressing mode using mp1l and mp1h. when data is written into the display data area, it is automatically read by the lcd driver which then generates the corresponding lcd driving signals. t o turn the display on or off, a "1" or a "0" is written to the corresponding bit of the display memory , respectiv ely. the fgure illustrates the mapping between the display memory and lcd pattern for the device. ?7 ?? ?5 ?? ?3 ?? ?1 ?0 com7 com? com5 com? com3 com? com1 com0 180h seg1 seg? seg30 seg31 181h 19eh 19fh seg0 lcd driver output the output number of the device lcd driver can be 32 4/328 or 28 4/288 . the lcd driver is "r" type only. the lcd clock source is from f sub , which can be either the lxt or lirc oscillator.
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lcd control register lcdc0 register bit 7 6 5 4 3 2 1 0 ? a ? e lcde ? type dtyc bias rsel ? rsel1 rsel0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 lcden : lcd enable/disable control 0: disable 1: enable note t hat t he l cd dri ver a nd a/ d c onverter shou ld not be e nabled si multaneously when the lcd output and a/d channel are shared with the same pin. bit 6 type : lcd w aveform t ype selection 0: t ype a 1: t ype b bit 5 dtyc : defne lcd duty 0: 1/4 duty (lcd com: com0~com3) 1: 1/8 duty (lcd com: com0~com7) note: if dtyc=1, then com4~com7 pins will be confgured as lcd com. if dtyc=0, then com4~com7 pins will be confgured as i/o. bit 4 bias : defne lcd bias 0: 1/3 bias 1: 1/4 bias bit 3 unimplemented, read as "0" bit 2~0 rsel2~rsel0 : t otal bias resistor r t selection 000: 1170k 001: 225k 010: 60k 011: quick charging mode, switch between 60k and 1170k. 1xx: quick charging mode, switch between 60k and 225k. note: the bias resistor for 1/3 bias is r t /3, 1/4 bias is r t /4. the devices provide low power quick char ging mode for lcd display . in quick charging m ode, t he l cd wi ll p rovide l cd b ias c urrent b y r t =60k, a t b eginning o f lcd display refreshes (i.e the moment on lcd com changes). after quick char ging time, the bias resistor will change to 225k/1170k. lcdc1 register bit 7 6 5 4 3 2 1 0 ? a ? e qct ? qct1 qct0 vlcd3 vlcd ? vlcd1 vlcd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 qct2~qct0 : quick charging time selection 000: 1t sub 001: 2t sub 010: 3t sub 011: 4t sub 100: 5t sub 101: 6t sub 110: 7t sub 111: 8t sub t sub =1/f sub bit 6 ~ 4 unimplemented, read as "0"
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 3 ~ 0 vlcd3~vlcd0 : vlcd selection 0000: 8/16v dd 0001: 9/16v dd 0010: 10/16v dd 0011: 11/16v dd 0100: 12/16v dd 0101: 13/16v dd 0110: 14/16 v dd 0111: 15/16v dd 1000~1111: 16/16v dd segcr0 register bit 7 6 5 4 3 2 1 0 ? a ? e seg7c seg ? c seg5c seg ? c seg3c seg ? c seg1c seg0c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 seg7c : select seg7 or pd7 0: seg7 1: pd7 bit 6 seg6c : select seg6 or pd6 0: seg6 1: pd6 bit 5 seg5c : select seg5 or pd5 0: seg5 1: pd5 bit 4 seg4c : select seg4 or pd4 0: seg4 1: pd4 bit 3 seg3c : select seg3 or pd3 0: seg3 1: pd3 bit 2 seg2c : select seg2 or pd2 0: seg2 1: pd2 bit 1 seg1c : select seg1 or pd1 0: seg1 1: pd1 bit 0 seg0c : select seg0 or pd0 0: seg0 1: pd0 segcr1 register bit 7 6 5 4 3 2 1 0 ? a ? e seg15c seg1 ? c seg13c seg1 ? c seg11c seg10c seg9c seg8c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 seg15c : select seg15 or pc7 0: seg15 1: pc7 bit 6 seg14c : select seg14 or pc6 0: seg14 1: pc6
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 5 seg13c : select seg13 or pc5 0: seg13 1: pc5 bit 4 seg12c : select seg12 or pc4 0: seg12 1: pc4 bit 3 seg11c : select seg11 or pc3 0: seg11 1: pc3 bit 2 seg10c : select seg10 or pc2 0: seg10 1: pc2 bit 1 seg9c : select seg9 or pc1 0: seg9 1: pc1 bit 0 seg8c : select seg8 or pc0 0: seg8 1: pc0 segcr2 register bit 7 6 5 4 3 2 1 0 ? a ? e seg ? 3c seg ?? c seg ? 1c seg ? 0c seg19c seg18c seg17c seg1 ? c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 seg23c : select seg23 or pg1 0: seg23 1: pg1 bit 6 seg22c : select seg22 or pg0 0: seg22 1: pg0 bit 5 seg21c : select seg21or pa2 0: seg21 1: pa2 bit 4 seg20c : select seg20 or pa0 0: seg20 1: pa0 bit 3 seg19c : select seg19 or pf7 0: seg19 1: pf7 bit 2 seg18c : select seg18 or pf6 0: seg18 1: pf6 bit 1 seg17c : select seg17 or pf5 0: seg17 1: pf5 bit 0 seg16c : select seg16 or pf4 0: seg16 1: pf4
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom segcr3 register bit 7 6 5 4 3 2 1 0 ? a ? e seg31c seg30c seg ? 9c seg ? 8c seg ? 7c seg ?? c seg ? 5c seg ?? c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 seg31c : select seg31 or pg7 0: seg31 1: pg7 bit 6 seg30c : select seg30 or pg6 0: seg30 1: pg6 bit 5 seg29c : select seg29 or pg5 0: seg29 1: pg5 bit 4 seg28c : select seg28 or pg4 0: seg28 1: pg4 bit 3 seg27c : select seg27 or pa7 0: seg27 1: pa7 bit 2 seg26c : select seg26 or pg3 0: seg26 1: pg3 bit 1 seg25c : select seg25 or pg2 0: seg25 1: pg2 bit 0 seg24c : select seg24 or pa6 0: seg24 1: pa6
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lcd waveform lcd display off mode com0 ~ com3 va all seng?ent outputs normal operation mode com0 com1 com? com3 all seg?ents a?e off com0 side seg?ents a?e o? all seng?ents a?e o? (othe? co??inations a?e o? itted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 f?a?e com1 side seg?ents a?e o? com? side seg?ents a?e o? com3 side seg?ents a?e o? com0?1 side seg?ents a?e o? com0?? side seg?ents a?e o? com0?3 side seg?ents a?e o? lcd d?ive? output C type a - 1/? duty? 1/3 bias note: v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3.
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lcd display off mode com0 ~ com3 va all seng?ent outputs normal operation mode com0 com1 com? com3 all seg?ents a?e off com0 side seg?ents a?e o? all seng?ents a?e o? (othe? co??inations a?e o? itted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 f?a?e com1 side seg?ents a?e o? com? side seg?ents a?e o? com3 side seg?ents a?e o? com0?1 side seg?ents a?e o? com0?? side seg?ents a?e o? com0?3 side seg?ents a?e o? lcd driver output C type b - 1/4 duty, 1/3 bias note: v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3.
rev. 1.00 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom com0 state1 (on) state? (off) lcd seg?ent 1 f?a?e v ss com1 v ss com? v ss com3 v ss com? v ss com5 v ss com? v ss com7 v ss v ss seg n v ss seg n+1 v ss seg n+? v ss seg n+3 va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd lcd driver output C type a - 1/8 duty, 1/4 bias
rev. 1.00 1?8 ?ove??e? ??? ?01? rev. 1.00 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom com0 state1 (on) state? (off) lcd seg?ent 1 f?a?e va vss vb vc vd com1 vss com? vss com3 vss com? vss com5 vss com? vss com7 vss vss seg n vss seg n+1 vss seg n+? vss seg n+3 va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd va vb vc vd lcd driver output C type b - 1/8 duty, 1/4 bias
rev. 1.00 130 ? ove ?? e ? ??? ? 01 ? rev. 1.00 131 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom led driver the device contains an led driver function of fering high current output drive capability which can be used to drive external leds. led driver operation the various i/o pins of device have a capability of providing led high current drive outputs, as shown in the accompanying table. led drive pins pd0~pd7 (high sou ? ce cu ?? ent) pe0~pe7 (high sink cu ?? ent) led driver register iohr0 register bit 7 6 5 4 3 2 1 0 ? a ? e iohs31 iohs30 iohs ? 1 iohs ? 0 iohs11 iohs10 iohs01 iohs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 iohr1 register bit 7 6 5 4 3 2 1 0 ? a ? e iohs71 iohs70 iohs ? 1 iohs ? 0 iohs51 iohs50 iohs ? 1 iohs ? 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 iohsn[1:0 ]: i oh capacity selection for pdn (n=0~7) 00: fullly source driving capacity of gpio 01: 1/3 source driving capacity of gpio 10: 1/4 source driving capacity of gpio 11: 1/6 source driving capacity of gpio
rev. 1.00 130 ?ove??e? ??? ?01? rev. 1.00 131 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom uart interface the device contai ns an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, universal asynchronous receiver and t ransmitter (uart) communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? transmitter and receiver enabled independently ? 2-byte deep fifo receive data buffer ? transmit and receive multiple interrupt generation sources: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect ? rx pin wake-up interrupt uart external pin interfacing to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx and rx pins are the uar t transmitter and receiver pins respectively . along with the uar ten bit, the txen and rxen bits, if set, will automatically setup these i/o or other pin-shared functional pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the tx or rx pins. when the tx or rx pin function is disabled by cle aring the uar ten and txen or rxen bit, the tx or rx pin can be used as a general purpose i/o or other pin-shared functional pin. uart data transfer scheme the block diagram s hows the overall data trans fer s tructure arrangement for the u art interface. the a ctual da ta t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he application program. the data will then be transferred to the t ransmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator . only the txr register is mapped onto the mcu data memory , the transmit shift register is not mapped and is therefore inaccessible to the application program.
rev. 1.00 13 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 133 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft r egister a t a ra te c ontrolled by t he b aud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu da ta me mory, t he re ceiver shift re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr/rxr register is used for both data transmission and data reception. msb lsb t?ans?itte? shift registe? msb lsb receive? shift registe? tx pin rx pin baud rate gene?ato? txr registe? rxr registe? buffe? mcu data bus f sys uart data transfer scheme uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr/ rxr data register. register name bit 7 6 5 4 3 2 1 0 usr perr ? f ferr oerr ridle rxif tidle txif ucr1 uarte ? b ? o pre ? prt stops txbrk rx8 tx8 ucr ? txe ? rxe ? brgh adde ? wake rie tiie teie txr/rxr txrx7 txrx ? txrx5 txrx ? txrx3 txrx ? txrx1 txrx0 brg brg7 brg ? brg5 brg ? brg3 brg ? brg1 brg0 uart register list
rev. 1.00 13? ?ove??e? ??? ?01? rev. 1.00 133 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below. bit 7 6 5 4 3 2 1 0 ? a ? e perr ? f ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error flag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is "0", it indicates a parity error has not been detected. when the fag is "1", it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise flag 0: no noise is detected 1: noise is detected the nf fla g is the noise fla g. whe n thi s read only fla g is "0", it indi cates no noise condition. when the fag is "1", it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error flag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is "0", it indicates that there is no framing error . when the fag is " 1", it indicates that a framing error has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error flag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is "0", it indicates that there is no overrun error . when the fag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register . the fag is cleared by a software sequence, which is a read to the s tatus regis ter u sr follow ed by an acces s to the rx r data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. when the fag is "1", it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is "1" indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.00 13 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 135 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is "0", it indicates that the rxr read data register is empty . when the fag is "1", it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r register , an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only fag is "0", it indicates that a transmission is in progress. this fag will be set to "1" when the txif fag is "1" and when there is no transmit data or break character being transmitted. when tidle is equal to "1", the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register ( txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is "0", it indicat es that the character is not transferred to the transmitter shift register . when the fag is "1", it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below. bit 7 6 5 4 3 2 1 0 ? a ? e uarte ? b ? o pre ? prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 "x" unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are in a foating state 1: enable uart. tx and rx pins function as uart pins the uar ten b it i s t he uar t e nable b it. w hen t his b it i s e qual t o "0 ", t he uar t wi ll be disabled and the rx pin as well as the tx pin will be set in a foating state. when the bit is equal to "1", the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration.
rev. 1.00 13? ?ove??e? ??? ?01? rev. 1.00 135 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 6 bno : number of data t ransfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to "1", a 9-bit data length format will be selected. if the bit is equal to "0", then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9 th bit of the received and transmitted data respectively. note: 1. if bno=1 (9-bit data transfer), parity function is enabled, the 9th bit of data is the parity bit which will not be transferred to rx8. 2. if bno=0 (8-bit data transfer), parity function is enabled, the 8th bit of data is the parity bit which will not be transferred to rx7. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to "1", the parity function will be enabled. if the bit is equal to "0", then the parity function will be disabled. bit 4 prt : parity t ype selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to "1", odd parity type will be selected. if the bit is equal to "0", then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determine s if one or two stop bits are to be used for the tx pin. when this bit is equal to "1", two stop bits are used. if this bit is equal to "0", then only one stop bit is used. bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is "0", there are no break characte rs and the tx pin operates normally . when the bit is "1", there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to "1", after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data t ransfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data t ransfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format.
rev. 1.00 13 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 137 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below. bit 7 6 5 4 3 2 1 0 ? a ? e txe ? rxe ? brgh adde ? wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enable control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be set in a foating state. if the txen bit is equal to "1" and the uar ten bit is also equal to "1", the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be set in a foating state. bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the bi t na med rxe n i s t he re ceiver e nable bi t. w hen t his bi t i s e qual t o "0", t he receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be set in a foating state. if the rxen bit is equal to "1" and the uar ten bit is also equal to "1", the receiver will be enabled and the rx pin will be controlled by the uar t. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be set in a foating state. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to "1", the high speed mode is selected. if the bit is equal to "0", the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detection function is disabled 1: address detection function is enabled the bi t na med adde n i s t he a ddress de tect fu nction e nable c ontrol bi t. w hen t his bit is equal to "1" , the address detect function is enabled. when it occurs, if the 8 th bit, which corresponds to rx7 if bno=0 or the 9 th bit, which corresponds to rx8 if bno=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 th or 9 th bit depending on the value of bno. if the address bit known as the 8 th or 9 th bit of the received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded.
rev. 1.00 13? ?ove??e? ??? ?01? rev. 1.00 137 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 3 wake : rx pin falling edge w ake-up uart function enable control 0: rx pin wake-up uart function is disabled 1: rx pin wake-up uart function is enabled this bit is used to control the wake-up uar t function when a falling edge on the rx pin occurs. note that this bit is only available when the uar t clock (f sys ) is switched off. there will be no rx pin wake-up uar t function if the uar t clock (f sys ) exists. if the w ake bit is set to 1 as the uar t clock (f sys ) is switched of f, a uar t wake- up request will be initiated when a falling edge on the rx pin occurs. when this request happens and the corresponding interrupt is enabled, an rx pin wake-up uar t interrupt will be generated to inform the mcu to wake up the uar t function by switching o n t he uar t c lock ( f sys ) v ia t he a pplication p rogram. ot herwise, t he uar t function can not resume even if there is a falling edge on the rx pin when the w ake bit is cleared to 0. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to "1" and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : t ransmitter idleinterrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to "1" and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to "1" and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t i nterrupt re quest fl ag wi ll be se t. if t his bi t i s e qual t o "0", t he uar t interrupt request fag will not be infuenced by the condition of the txif fag. txr/rxr register the txr/rxr register is the data register which is used to store the data to be transmitted on the tx pin or being received from the rx pin. bit 7 6 5 4 3 2 1 0 ? a ? e txrx7 txrx ? txrx5 txrx ? txrx3 txrx ? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown bit 7~0 txrx7~txrx0 : uart t ransmit/receive data bit 7 ~ bit 0
rev. 1.00 138 ? ove ?? e ? ??? ? 01 ? rev. 1.00 139 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud rate generator. t he baud ra te is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register , n, which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f sys / [ ?? ( ? +1)] f sys / [1 ? ( ? +1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. brg register bit 7 6 5 4 3 2 1 0 ? a ? e brg7 brg ? brg5 brg ? brg3 brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown bit 7~0 brg7~brg0 : baud ratevalues by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. note: 1. baud rate=f sys / [64 (n+1)] if brgh=0. 2. baud rate=f sys / [16 (n+1)] if brgh=1. calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to "0" determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br= f sys / [64 (n+1)] re-arranging this equation gives n=[ f sys / (br64)] - 1 giving a value for n=[4000000 / (480064)] - 1=12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br=4000000 / [64 (12 + 1)]=4808 therefore the error is equal to (4808 - 4800) / 4800=0.16% the following table shows actual values of baud rate and error values for the two values of brgh.
rev. 1.00 138 ?ove??e? ??? ?01? rev. 1.00 139 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom baud rate k/bps f sys =8mhz baud rates for brgh=0 baud rates for brgh=1 brg kbaud error (%) brg kbaud error (%) 0.3 1. ? 103 1. ? 0 ? 0.1 ? ? . ? 51 ? . ? 0 ? 0.1 ? ? 07 ? . ? 0 ? 0.1 ? ? .8 ? 5 ? .808 0.1 ? 103 ? .808 0.1 ? 9. ? 1 ? 9. ? 15 0.1 ? 51 9. ? 15 0.1 ? 19. ? ? 17.8857 - ? .99 ? 5 19. ? 31 0.1 ? 38. ? ? ? 1. ?? 7 8.51 1 ? 38. ??? 0.1 ? 57. ? 1 ?? .500 8.51 8 55.55 ? -3.55 115. ? 0 1 ? 5 8.51 3 1 ? 5 8.51 ? 50 1 ? 50 0 baud rates and error values uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding b no, pr t, pr en, a nd st ops bi ts in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart interface the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins. when the uar t functi on is disabled the buf fer will be reset to an empty condition, at the same time discarding any remai ning residual data. disabling the uar t will also reset the error and status fags with bits txen, rxen, txbrk, rxif , oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediate ly suspended and the uar t will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration.
rev. 1.00 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom data, parity and stop bit selection the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit, which is the msb of the data byte, identife s the frame as an address character or data if the address detect function is enable d. the number of stop bits, which can be either one or two, is independent of the data length and are only to be used for t ransmitter. there is only one stop bit for receiver. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. bit 0 8-?it data fo??at bit 1 stop bit ?ext sta?t bit sta?t bit pa?ity bit bit ? bit 3 bit ? bit 5 bit ? bit 7 bit 0 9-?it data fo??at bit 1 sta?t bit bit ? bit 3 bit ? bit 5 bit ? stop bit ?ext sta?t bit pa?ity bit bit 8 bit 7 uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s de fned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to the i/o or other pin-shared function.
rev. 1.00 1?0 ?ove??e? ??? ?01? rev. 1.00 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the leas t s ignificant bit firs t. in the trans mit mode, the tx r regis ter forms a buf fer betw een the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, prt, pren and stops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the uart transmitter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif is "0", data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: ? a usr register access ? a txr register write execution the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register , which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: ? a usr register access ? a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized.
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom uart receiver the uart is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr register . if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receive r core lies the receive serial shift register , commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate , while the main receive serial shifter operates at the baud rate . after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register , if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin to the shift register , with the lea st signifcant bit lsb frst. the rxr register is a two byte deep fifo data buf fer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of bno, prt and pren bits to defne the word length and parity type. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received, the following sequence of events will occur: ? the rxif bit in the usr register will be set when the rxr register has data available. there will be at most one more characters available before an overrun error occurs. ? when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: ? a usr register access ? an rxr register read execution
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom receive break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specified by the values programmed into the bno and plus ing one s top bit. if the break is much longer than 13 bit times , the reception w ill be c onsidered a s c omplete a fter t he n umber o f b it t imes sp ecifed b y b no a nd p lusing o ne st op bit. the rxif bit is set, ferr is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the ridle bit is set. a break is regarded as a character that contains only zeros with the ferr fag set. if a long break signal has been detected, the receiver will regard it as a data frame including a start bit, data bits and the invalid stop bit and the ferr fag will be set. the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie bit is "1", when a word is transferred from the receive shift re gister, rsr, t o t he re ceive da ta re gister, rxr. an ove rrun e rror c an a lso ge nerate a n interrupt if rie is "1". managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr flag the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register.
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom noise error C nf flag over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr flag the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are select ed, only the frst stop bit is detecte d, it must be high. if the frst stop bit is low , the ferr fag will be set. the ferr fag and the received data will be recorded in the usr and rxr registers respectively, and the fag is cleared in any reset. parity error C perr flag the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren bit is "1", and if the parity type, odd or e ven i s sel ected. t he re ad onl y perr fag a nd t he re ceived da ta wi ll be re corded i n the usr and rxr registers respectively . it is cleared on any reset, it should be noted that the fags, ferr and perr, in the usr register should frst be read by the applic ation program before reading the data word. uart module interrupt structure several individual u art conditions can generate a u art interrupt. when these conditions exist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter da ta re gister e mpty, t ransmitter i dle, re ceiver da ta a vailable, re ceiver ove rrun, a ddress detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. four of these conditions have the corresponding usr register flags which will generate a uar t interrupt if its associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whic h is al so a uar t i nterrupt source, does not have an associa ted fag, but will generate a uar t interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register . an rx pin wake-up, which is also a uar t interrupt source, does not have an associated fag, but will generate a uar t interrupt if the uar t clock (f sys ) is switched of f and the w ake and rie bits in the ucr2 register are set when a falling edge on the rx pin occurs. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be di sabled or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed.
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom t?ans?itte? e?pty flag txif usr registe? t?ans?itte? idle flag tidle receive? ove??un flag oerr receive? data availa?le rxif adde? rx pin wake-up wake 0 1 0 1 0 1 rx7 if b?o=0 rx8 if b?o=1 ucr? registe? or rie 0 1 tiie 0 1 teie 0 1 uart inte??upt request flag uarf ucr? registe? uare i?tc? registe? emi i?tc0 registe? uart interrupt scheme address detect mode setting t he ad dress de tect mo de b it, adde n, i n t he uc r2 r egister, e nables t his sp ecial m ode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data a vailable interrupt, which is requested by the rxif fag. if the adden bit is "1", then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit must also be enabled for correct interrupt generation. this highest address bit is the 9 th bit if bn o bit is " 1" or the 8th bit if bno bit is "0". if this bit is high, then the received word will be defned as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is "0", then a receiver data a vailable interrupt will be generated each time the rxif flag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit pren to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 1 adden bit function
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom uart power down and wake-up when the uar t clock (f sys ) is switched of f, the uar t will cease to function, all clock sources to the module are shutdown. if the uar t clock (f sys ) is of f while a transmission is still in progress, then the transmission will be paused until the uar t clock (f sys ) source derived from the microcontroller is activated. in a similar way , if the device executes the "hal t" instruction and swi tches o ff t he sy stem c lock wh ile r eceiving d ata, t hen t he r eception o f d ata wi ll l ikewise be paused. when the device enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and recei ve registers, as well as the brg register will not be af fected. it is recommended to make sure first that the ua rt data transmis sion or reception has been finished before the microcontroller enters the idle or sleep mode. the u art function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set when the uar t clock (f sys ) is of f, then a fallin g edge on the rx pin will trigger an rx pin wake-up uar t interrupt. note that as i t t akes c ertain syst em c lock c ycles a fter a wa ke-up, be fore nor mal m icrocontroller ope ration resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uar t interrupt enable bit, uare, must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and inter nal interrupt functions. the external interrupts are generated by the action of the external int0~int3 pins, while the internal interrupts are generated by various internal functions such as the t imer modules, t ime bases, serial interface module , low v oltage detector , eeprom, uart and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory . the registers fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi4 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupts trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes glo ? al emi i ? tn pin i ? tne i ? tnf n=0~3 a/d conve ? te ? ade adf multi-function mfne mfnf n=0~ ? ti ? e base tbne tbnf n=0~1 lvd lve lvf eeprom dee def uart uare uarf sim sime simf tm tnpe tnpf n=0~3 tnae tnaf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 i ? teg i ? t3s1 i ? t3s0 i ? t ? s1 i ? t ? s0 i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 i ? tc0 mf0f i ? t1f i ? t0f mf0e i ? t1e i ? t0e emi i ? tc1 adf mf3f mf ? f mf1f ade mf3e mf ? e mf1e i ? tc ? mf ? f i ? t3f i ? t ? f uarf mf ? e i ? t3e i ? t ? e uare i ? tc3 simf sime mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi ? t ? af t ? pf t ? ae t ? pe mfi3 t3af t3pf t3ae t3pe mfi ? tb1f tb0f def lvf tb1e tb0e dee lve interrupt register list
rev. 1.00 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom integ register bit 7 6 5 4 3 2 1 0 ? a ? e i ? t3s1 i ? t3s0 i ? t ? s1 i ? t ? s0 i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1~int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 5~4 int2s1~int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1~int1s0 : interrupt edgecontrol for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register bit 7 6 5 4 3 2 1 0 ? a ? e mf0f i ? t1f i ? t0f mf0e i ? t1e i ? t0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 int1f : external interrupt 1 request flag 0: no request 1: interrupt request bit 4 int0f : external interrupt 0 request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 2 int1e : external interrupt 1 control 0: disable 1: enable bit 1 int0e : exte rnal interrupt 0 control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.00 1?8 ?ove??e? ??? ?01? rev. 1.00 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom intc1 register bit 7 6 5 4 3 2 1 0 ? a ? e adf mf3f mf ? f mf1f ade mf3e mf ? e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 mf1e : multi-function interrupt 1 control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 ? a ? e mf ? f i ? t3f i ? t ? f uarf mf ? e i ? t3e i ? t ? e uare r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf4f : multi-function interrupt 4 request flag 0: no request 1: interrupt request bit 6 int3f : external interrupt 3 request flag 0: no request 1: interrupt request bit 5 int2f : external interrupt 2 request flag 0: no request 1: interrupt request bit 4 uarf : uart interrupt request flag 0: no request 1: interrupt request bit 3 mf4e : multi-function interrupt 4 control 0: disable 1: enable
rev. 1.00 150 ? ove ?? e ? ??? ? 01 ? rev. 1.00 151 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom bit 2 int3e : external interrupt 3 control 0: disable 1: enable bit 1 int2e : external interrupt 2 control 0: disable 1: enable bit 0 uare : uart interrupt control 0: disable 1: enable intc3 register bit 7 6 5 4 3 2 1 0 ? a ? e simf sime r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as "0" bit 4 simf : serial interface module interrupt request flag 0: no request 1: interrupt request bit 3~1 unimplemented, read as "0" bit 0 sime : serial interface module control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 ? a ? e t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af : tm0 ccra comparator interrupt request flag 0: no request 1: interrupt request bit 4 t0pf : tm0 ccrp comparator interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t0ae : tm0 ccra comparator interrupt control 0: disable 1: enable bit 0 t0pe : tm0 ccrp comparator interrupt control 0: disable 1: enable
rev. 1.00 150 ?ove??e? ??? ?01? rev. 1.00 151 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom mfi1 register bit 7 6 5 4 3 2 1 0 ? a ? e t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t1af : tm1 ccra comparator interrupt request flag 0: no request 1: interrupt request bit 4 t1pf : tm1 ccrp comparator interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t1ae : tm1 ccra comparator interrupt control 0: disable 1: enable bit 0 t1pe : tm1 ccrp comparator interrupt control 0: disable 1: enable mfi2 register bit 7 6 5 4 3 2 1 0 ? a ? e t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t2af : tm2 ccra comparator interrupt request flag 0: no request 1: interrupt request bit 4 t2pf : tm2 ccrp comparator interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t2ae : tm2 ccra comparator interrupt control 0: disable 1: enable bit 0 t2pe : tm2 ccrp comparator interrupt control 0: disable 1: enable
rev. 1.00 15 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 153 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom mfi3 register bit 7 6 5 4 3 2 1 0 ? a ? e t3af t3pf t3ae t3pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t3af : tm3 ccra comparator interrupt request flag 0: no request 1: interrupt request bit 4 t3pf : tm3 ccrp comparator interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t3ae : tm3 ccra comparator interrupt control 0: disable 1: enable bit 0 t3pe : tm3 ccrp comparator interrupt control 0: disable 1: enable mfi4 register bit 7 6 5 4 3 2 1 0 ? a ? e tb1f tb0f def lvf tb1e tb0e dee lve r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t imer base 1 interrupt request flag 0: no request 1: interrupt request bit 6 tb0f : t imer base 0 interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request flag 0: no request 1: interrupt request bit 3 tb1e : t imer base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t imer base 0 interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.00 15? ?ove??e? ??? ?01? rev. 1.00 153 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p , comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.00 15 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 155 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom inte??upt ?a?e request flags ena?le bits maste? ena?le vecto? emi auto disa?led in isr p?io?ity high low inte??upts contained within multi-function inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi sim simf sime 30h tm0 a t0af t0ae tm1 p t1pf t1pe tm? a t?af t?ae tm3 p t3pf t3pe 0?h i?t0 pin i?t0f i?t0e emi ?0h uart uarf uare emi emi 08h i?t1 pin i?t1f i?t1e inte??upt ?a?e request flags ena?le bits emi 0ch m. funct. 0 mf0f mf0e emi 10h m. funct. 1 mf1f mf1e emi 1?h m. funct. ? mf?f mf?e emi 18h m. funct. 3 mf3f mf3e ??h i?t?e emi tm0 p t0pf t0pe tm3 a t3af tm1 a t1af t1ae tm? p t?pf t?pe t3ae eeprom dee def lvd lvf lve i?t? pin i?t?f emi i?t3 pin i?t3f i?t3e ?8h emi m. funct. ? mf?f mf?e ?ch 1ch a/d conve?te? adf ade emi ti?e base 1 tb1f tb1e ti?e base 0 tb0f tb0e interrupt structure external interrupt the external interrupts are controlled by signal transitions on the pins int0~int3. an external interrupt request will take place when the external interrupt request fags, int0f~int3f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . t o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, e mi, a nd r espective e xternal i nterrupt e nable b it, i nt0e~int3e, must first be set. additionally the correct interrupt edge type mus t be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the s tack is not full and the correct trans ition type appears on the external i nterrupt p in, a su broutine c all t o t he e xternal i nterrupt v ector, wi ll t ake p lace. w hen t he interrupt is serviced, the external interrupt request flags, int0f~int3f , will be automatically reset and t he emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts. not e t hat any pull - high resistor selec tions on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interr upt. a choice of either rising or falling or both edge types can be chosen to trigger an extern al interru pt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.00 15? ?ove??e? ??? ?01? rev. 1.00 155 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. multi-function interrupts within this device there are three multi-function interrupts. unlike the other independent interrupts, these int errupts have no i ndependent sourc e, but rathe r are form ed from other exi sting int errupt sources, namely the tm interrupts, eeprom interrupt lvd interrupt and t ime base interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program. serial interface module interrupt the serial interface module interrupt is also known as the sim interrupt. a sim interrupt request will take place when the sim interrupt request flag, simf , is set, which occurs when a byte of data has been received or transmitted by the sim interface, an i 2 c address match or i 2 c time-out occurrence. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must first be set. when the interrup t is enabled, the stack is not full and any of the above described situations occurs, a subrout ine c all t o t he sim i nterrupt ve ctor, wi ll t ake pl ace. w hen t he sim int erface int errupt i s serviced, the inter rupt request fag, simf , will be automatically reset and the emi bit will be cleared to disable other interrupts. uart interrupt several individual uar t conditions can generate a uar t interrupt. when these conditions exist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. t o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, emi, and uar t interrupt enable bit, uare, mus t frst be set. when the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the uar t interrupt vector will take place. when the interrupt is serviced, the uart interrupt fag, uarf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. however , the usr register fags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart section.
rev. 1.00 15 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 157 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom time base interrupts the t ime bas e interrupts are contained w ithin the m ulti-function interrupt. the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are c ontrolled b y t he o verfow si gnals f rom t heir r espective t imer f unctions. w hen t hese h appens their respective interrupt request fags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bi ts, tb0e or tb1e, and associ ated multi-functi on interrupt enable bit, must fi rst be set. when the interrup t is enabled, the stack is not full and the t ime base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the tbnf fag will not be automatically cleared, it has to be cleared by the application program. the purpose of t he t ime base inte rrupt i s t o provi de an i nterrupt si gnal at fixe d t ime peri ods. their clock source originates from the internal clock source f tb , this f tb input clock passes through a di vider, t he di vision ra tio of whi ch i s se lected by progra mming t he a ppropriate bi ts i n t he t bc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 ? a ? e tbo ? tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : t ime base 0 and t ime base 1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select t ime base 1 t ime-out period 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 /f tb bit 3 unimplemented, read as "0" bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb
rev. 1.00 15? ?ove??e? ??? ?01? rev. 1.00 157 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom f sys /? m u x f tb ti?e base 0 inte??upt ti?e base 1 inte??upt tb0? ~ tb00 tb11 ~ tb10 ? 8 ~ ? 15 ? 1? ~ ? 15 lirc f tbc tbck bit m u x fsubc fsub?~fsub0 ?its lxt time base interrupt eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack i s n ot f ull a nd a n e eprom w rite c ycle e nds, a su broutine c all t o t he r espective e eprom interrupt vector will take place. when the eeprom interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. timer module interrupts each of the compact t ype tm and periodic t ype tm has two interru pts. all of the tm interrupts are contained within the multi-function interrupts. for the compact t ype tm and the periodic t ype tm, each has two interrupt request fags of tnpf and tnaf and two enable bits of tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 158 ? ove ?? e ? ??? ? 01 ? rev. 1.00 159 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltag e may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. t o return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 158 ?ove??e? ??? ?01? rev. 1.00 159 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom low voltage detector C lvd the device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 ? a ? e lvdo lvde ? vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2~vlvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 1 ? 0 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?1 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd voltage with a pre-specifed voltage level stored in the l vdc register . this has a range of between 2.0v and 4 .0v. w hen t he p ower su pply v oltage, v dd v oltage f alls b elow t his p re-determined v alue, the l vdo bi t wi ll be se t hi gh i ndicating a l ow po wer sup ply vo ltage c ondition. t he l ow v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down, the low voltage detector will remain active if the l vden bit is high. after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. v dd lvde? lvdo v lvd t lvds lvd operation the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt, p roviding an a lternative m eans o f l ow v oltage d etection, i n a ddition t o p olling t he l vdo b it. t he i nterrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down, the low voltage detector will remain active if the lvden bit is high. in this case , the l vf interrupt request fag wil l be set , causing an interrupt to be generated if v dd voltage falls below the preset l vd voltage. this will cause the device to wake- up from the sleep or idle mode, however if the low v oltage detector wake up function is not required t hen t he l vf f lag sh ould b e f irst se t h igh b efore t he d evice e nters t he sl eep o r i dle mode.when l vd function is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.00 1?0 ?ove??e? ??? ?01? rev. 1.00 1 ? 1 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program, all options must be defned for proper system function, the details of which are shown in the table. no. options 1 high speed syste ? oscillato ? selection f h - hxt o ? hirc
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?3 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom application circuits vdd vss an0~an9 pa0~pa7 pb0~pb5 pc0~pc7 pd0~pd7 pe0~pe7 pf4~pf7 pg0~pg7 seg0~seg31 com0~com7 tx rx sdo sdi/sda scs sck/scl 0.1 f v dd see oscillator section xt1 xt2 osc circuit
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 3 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?5 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek m icrocontrollers. t his fe ature i s e specially use ful for out put port bi t progra mming whe re individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" i nstructions r espectively. t he f eature r emoves t he n eed f or p rogrammers t o fr st r ead t he 8 -bit output port, manip ulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 5 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom instruction set summary the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov ? sc addm a ? [ ? ] add acc to data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov ? sc adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 ? ote z ? c ? ac ? ov ? sc sub a ? x su ? t ? act i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov ? sc ? cz subm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc ? cz sbc a ? x su ? t ? act i ?? ediate data f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbcm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc ? cz daa [ ? ] deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 ? ote c logic operation a ? d a ? [ ? ] logical a ? d data me ? o ? y to acc 1 z or a ? [ ? ] logical or data me ? o ? y to acc 1 z xor a ? [ ? ] logical xor data me ? o ? y to acc 1 z a ? dm a ? [ ? ] logical a ? d acc to data me ? o ? y 1 ? ote z orm a ? [ ? ] logical or acc to data me ? o ? y 1 ? ote z xorm a ? [ ? ] logical xor acc to data me ? o ? y 1 ? ote z a ? d a ? x logical a ? d i ?? ediate data to acc 1 z or a ? x logical or i ?? ediate data to acc 1 z xor a ? x logical xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 ? ote z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement i ? ca [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc 1 z i ? c [ ? ] inc ? e ? ent data me ? o ? y 1 ? ote z deca [ ? ] dec ? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] dec ? e ? ent data me ? o ? y 1 ? ote z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 ? one rr [ ? ] rotate data me ? o ? y ? ight 1 ? ote ? one rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 ? ote c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 ? one rl [ ? ] rotate data me ? o ? y left 1 ? ote ? one rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 ? ote c
rev. 1.00 1 ?? ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?7 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 ? one mov [ ? ] ? a move acc to data me ? o ? y 1 ? ote ? one mov a ? x move i ?? ediate data to acc 1 ? one bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 ? ote ? one set [ ? ].i set ? it of data me ? o ? y 1 ? ote ? one branch operation jmp add ? ju ? p unconditionally ? ? one sz [ ? ] skip if data me ? o ? y is ze ? o 1 ? ote ? one sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 ? ote ? one sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 ? ote ? one s ? z [ ? ] skip if data me ? o ? y is not ze ? o 1 ? ote ? one s ? z [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 ? ote ? one siz [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one sdz [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one siza [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one sdza [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one call add ? su ?? outine call ? ? one ret retu ? n f ? o ? su ?? outine ? ? one ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? ? one reti retu ? n f ? o ? inte ?? upt ? ? one table read operation tabrd [ ? ] read table (specifc page) to tblh and data memory ? ? ote ? one tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? ? ote ? one itabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory ? ? ote ? one itabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y ? ? ote ? one miscellaneous ? op ? o ope ? ation 1 ? one clr [ ? ] clea ? data me ? o ? y 1 ? ote ? one set [ ? ] set data me ? o ? y 1 ? ote ? one clr wdt clea ? watchdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 ? ote ? one swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 ? one halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt" instruction the t o and pdf fags may be af fected by the execution status. the t o and pdf fa gs a re c leared a fter t he "cl r w dt" i nstructions i s e xecuted. ot herwise t he t o a nd pdf fags remain unchanged.
rev. 1.00 1?? ?ove??e? ??? ?01? rev. 1.00 1 ? 7 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom extended instruction set the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a ? [ ? ] add data me ? o ? y to acc ? z ? c ? ac ? ov ? sc laddm a ? [ ? ] add acc to data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ladc a ? [ ? ] add data me ? o ? y to acc with ca ?? y ? z ? c ? ac ? ov ? sc ladcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y ? ? ote z ? c ? ac ? ov ? sc lsub a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc ? z ? c ? ac ? ov ? sc ? cz lsubm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ? cz lsbc a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? z ? c ? ac ? ov ? sc ? cz lsbcm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ? cz ldaa [ ? ] deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y ? ? ote c logic operation la ? d a ? [ ? ] logical a ? d data me ? o ? y to acc ? z lor a ? [ ? ] logical or data me ? o ? y to acc ? z lxor a ? [ ? ] logical xor data me ? o ? y to acc ? z la ? dm a ? [ ? ] logical a ? d acc to data me ? o ? y ? ? ote z lorm a ? [ ? ] logical or acc to data me ? o ? y ? ? ote z lxorm a ? [ ? ] logical xor acc to data me ? o ? y ? ? ote z lcpl [ ? ] co ? ple ? ent data me ? o ? y ? ? ote z lcpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc ? z increment & decrement li ? ca [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc ? z li ? c [ ? ] inc ? e ? ent data me ? o ? y ? ? ote z ldeca [ ? ] dec ? e ? ent data me ? o ? y with ? esult in acc ? z ldec [ ? ] dec ? e ? ent data me ? o ? y ? ? ote z rotate lrra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc ? ? one lrr [ ? ] rotate data me ? o ? y ? ight ? ? ote ? one lrrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc ? c lrrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y ? ? ote c lrla [ ? ] rotate data me ? o ? y left with ? esult in acc ? ? one lrl [ ? ] rotate data me ? o ? y left ? ? ote ? one lrlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc ? c lrlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y ? ? ote c data move lmov a ? [ ? ] move data me ? o ? y to acc ? ? one lmov [ ? ] ? a move acc to data me ? o ? y ? ? ote ? one bit operation lclr [ ? ].i clea ? ? it of data me ? o ? y ? ? ote ? one lset [ ? ].i set ? it of data me ? o ? y ? ? ote ? one
rev. 1.00 1 ? 8 ? ove ?? e ? ??? ? 01 ? rev. 1.00 1?9 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected branch lsz [ ? ] skip if data me ? o ? y is ze ? o ? ? ote ? one lsza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc ? ? ote ? one ls ? z [ ? ] skip if data me ? o ? y is not ze ? o ? ? ote ? one lsz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o ? ? ote ? one ls ? z [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o ? ? ote ? one lsiz [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o ? ? ote ? one lsdz [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o ? ? ote ? one lsiza [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? ? ote ? one lsdza [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? ? ote ? one table read ltabrd [ ? ] read ta ? le to tblh and data me ? o ? y 3 ? ote ? one ltabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y 3 ? ote ? one litabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory 3 ? ote ? one litabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y 3 ? ote ? one miscellaneous lclr [ ? ] clea ? data me ? o ? y ? ? ote ? one lset [ ? ] set data me ? o ? y ? ? ote ? one lswap [ ? ] swap ni ?? les of data me ? o ? y ? ? ote ? one lswapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc ? ? one note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.00 1?8 ?ove??e? ??? ?01? rev. 1.00 1 ? 9 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c , s c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.00 170 ? ove ?? e ? ??? ? 01 ? rev. 1.00 171 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.00 170 ?ove??e? ??? ?01? rev. 1.00 171 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none
rev. 1.00 17 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 173 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none
rev. 1.00 17? ?ove??e? ??? ?01? rev. 1.00 173 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c
rev. 1.00 17 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 175 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sbc a, x subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none
rev. 1.00 17? ?ove??e? ??? ?01? rev. 1.00 175 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none snz [m] skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.00 17 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 177 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.00 17? ?ove??e? ??? ?01? rev. 1.00 177 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.00 178 ? ove ?? e ? ??? ? 01 ? rev. 1.00 179 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladd a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c laddm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c land a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z landm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z lclr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none lclr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none
rev. 1.00 178 ?ove??e? ??? ?01? rev. 1.00 179 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lcpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z lcpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z ldaa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c ldec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z ldeca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z linc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z linca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.00 180 ? ove ?? e ? ??? ? 01 ? rev. 1.00 181 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lmov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none lmov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none lor a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z lorm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z lrl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none lrla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none lrlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c lrlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c
rev. 1.00 180 ?ove??e? ??? ?01? rev. 1.00 181 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lrr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none lrra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none lrrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c lrrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c lsbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z lsbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.00 18 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 183 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lsdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none lsdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none lset [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none lset [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none lsiz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none lsiza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none lsnz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none
rev. 1.00 18? ?ove??e? ??? ?01? rev. 1.00 183 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lsnz [m] skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none lsub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lsubm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lswap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none lswapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none lsz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none lsza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none
rev. 1.00 18 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 185 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom lsz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none ltabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none ltabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none lxor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z lxorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z
rev. 1.00 18? ?ove??e? ??? ?01? rev. 1.00 185 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 18 ? ? ove ?? e ? ??? ? 01 ? rev. 1.00 187 ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a ? 0.354 bsc ? b ? 0.276 bsc ? c ? 0.354 bsc ? d ? 0.276 bsc ? e ? 0.020 bsc ? f 0.007 0.009 0.0 11 g 0.053 0.055 0.057 h ? ? 0.063 i 0.002 ? 0.006 j 0.018 0.024 0.030 k 0.004 ? 0.008 0 D 7 symbol dimensions in mm min. nom. max. a ? 9.000 bsc ? b ? 7.000 bsc ? c ? 9.000 bsc ? d ? 7.000 bsc ? e ? 0.500 bsc ? f 0.170 0.220 0.270 g 1.350 1.400 1.450 h ? ? 1.600 i 0.050 ? 0.150 j 0.450 0.600 0.750 k 0.090 ? 0.200 0 D 7
rev. 1.00 18? ?ove??e? ??? ?01? rev. 1.00 187 ? ove ?? e ? ??? ? 01 ? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom 52-pin lqfp (14mm14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0. ??? 0. ? 30 0. ? 38 b 0.5 ? 7 0.551 0.555 c 0. ??? 0. ? 30 0. ? 38 d 0.5 ? 7 0.551 0.555 e D 0.039 bsc D f 0.015 D 0.019 g 0.053 0.055 0.057 h 0.0 ? 3 i 0.00 ? 0.008 j 0.018 0.030 k 0.005 0.007 0 D 7 symbol dimensions in mm min. nom. max. a 15.80 1 ? .00 1 ? . ? 0 b 13.90 1 ? .00 1 ? .10 c 15.80 1 ? .00 1 ? . ? 0 d 13.90 1 ? .00 1 ? .10 e 1.00 bsc f 0.39 0. ? 8 g 1.35 1. ? 0 1. ? 5 h 1. ? 0 i 0.05 0. ? 0 j 0. ? 5 0.75 k 0.13 0.18 0 D 7
rev. 1.00 188 ? ove ?? e ? ??? ? 01 ? rev. 1.00 pb ?ove??e? ??? ?01? HT67F4892 enhanced a/d flash mcu with lcd & eeprom HT67F4892 enhanced a/d flash mcu with lcd & eeprom copy ? ight ? ? 01 ? ? y holtek semico ? ductor i ? c. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e accu ? ate at the ti ? e of pu ? lication. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that such applications will ? e suita ? le without fu ? the ? ? odification ? no ? ? eco ?? ends the use of its p ? oducts fo ? application that ? ay p ? esent a ? isk to hu ? an life due to ? alfunction o ? othe ? wise. holtek's p ? oducts a ? e not autho ? ized fo ? use as c ? itical co ? ponents in life suppo ? t devices o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek.co ? /zh/.

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